Hello Wolfgang & list,
I have "ported" U-boot to a in house made board with Numonyx Axcell P33/P30 256-Mbit 65nm flash chips.
After some time :( searching for bugs in our board or soft, we have discovered that those chips have a small but annoying bug, documented in "Numonyx Axcell P33/P30 256-Mbit Specification Update"
It states : When customer uses [...] block unlock, the block lock status might be altered inadvertently. Lock status might be set to either 01h or 03h unexpectedly (00h as expected data), which leads to program/erase failure on certain blocks.
A working workaround is given, which I have applied and tested with success.
Signed-off-by: Philippe De Muyter phdm@macqel.be
--- drivers/mtd/cfi_flash.c | 27 ++++++++++++++++++++------- 1 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 3267c5d..0931137 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -1347,16 +1347,29 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) switch (info->vendor) { case CFI_CMDSET_INTEL_PROG_REGIONS: case CFI_CMDSET_INTEL_STANDARD: - case CFI_CMDSET_INTEL_EXTENDED: - flash_write_cmd (info, sector, 0, - FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + case CFI_CMDSET_INTEL_EXTENDED: { + unsigned short cmd; + if (prot) - flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_SET); + cmd = FLASH_CMD_PROTECT_SET; else + cmd = FLASH_CMD_PROTECT_CLEAR; + /* see errata + "Numonyx Axcell P33/P30 Specification Update" :) */ + flash_write_cmd (info, sector, 0, FLASH_CMD_READ_ID); + if (!flash_isequal (info, sector, FLASH_OFFSET_PROTECT, + prot)) { + /* cmd must come before 20us after FLASH_CMD_PROTECT */ + /* Disable interrupts which might cause a timeout here */ + int flag = disable_interrupts (); flash_write_cmd (info, sector, 0, - FLASH_CMD_PROTECT_CLEAR); + FLASH_CMD_PROTECT); + flash_write_cmd (info, sector, 0, cmd); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + } + } break; case CFI_CMDSET_AMD_EXTENDED: case CFI_CMDSET_AMD_STANDARD: