On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
Add the structures for the SDRAM controller on Arria10.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@kernel.org Cc: Chin Liang See chin.liang.see@intel.com Cc: Tien Fong skywindctf@gmail.com
arch/arm/mach-socfpga/include/mach/sdram_a10.h | 380 +++++++++++++++++++++++++ 1 file changed, 380 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_a10.h
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_a10.h b/arch/arm/mach-socfpga/include/mach/sdram_a10.h new file mode 100644 index 0000000..0403531 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram_a10.h @@ -0,0 +1,380 @@ +/*
- Copyright (C) 2015 Altera Corporation <www.altera.com>
- SPDX-License-Identifier: GPL-2.0
- */
+#ifndef _SOCFPGA_SDRAM_A10_H_ +#define _SOCFPGA_SDRAM_A10_H_
#ifdef[space] and #define[space] , drop the [tab]
+#ifndef __ASSEMBLY__
[...]
+#define IO48_MMR_CTRLCFG1_DBC3_ENABLE_DM (1 << 30)
Use the BIT(n) macro instead of (1 << n).
+#define IO48_MMR_CTRLCFG1_DBC2_ENABLE_DM (1 << 29) +#define IO48_MMR_CTRLCFG1_DBC1_ENABLE_DM (1 << 28) +#define IO48_MMR_CTRLCFG1_DBC0_ENABLE_DM (1 << 27)
[...]