Re: [U-Boot] [PATCH V2 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

4 Feb 2013

On 19:59-20130204, R Sricharan wrote:
...
Change OPP settings as per the latest 0.4 version of
addendum for OMAP5430 ES2.0
-->please be clear that these are for OPP_NOM. FYI, latest documentation
is 0.5 rev which was released in Jan, considering this patch was send in
Feb, might be good to cross verify any updates.
in addition, I suspect TRM was referred for certain DPLLs as well?
...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap-common/clocks-common.c |    4 +
 arch/arm/cpu/armv7/omap4/hw_data.c             |  142 +++++++-------
 arch/arm/cpu/armv7/omap5/hw_data.c             |  242 +++++++++++++++---------
 arch/arm/include/asm/arch-omap5/clocks.h       |    4 +
 arch/arm/include/asm/omap_common.h             |    6 +-
 5 files changed, 241 insertions(+), 157 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 88e5336..164253c 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params)
   	writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
   if (params->m7_h14 >= 0)
   	writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);

if (params->h21 >= 0)
writel(params->h21, &dpll_regs->cm_div_h21_dpll);

if (params->h22 >= 0)
writel(params->h22, &dpll_regs->cm_div_h22_dpll);
if (params->h23 >= 0)
writel(params->h23, &dpll_regs->cm_div_h23_dpll);
if (params->h24 >= 0)
writel(params->h24, &dpll_regs->cm_div_h24_dpll);



}
static inline void do_bypass_dpll(u32 const base)
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 892d016..b01bf5d 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -51,113 +51,113 @@ struct omap_sys_ctrl_regs const **ctrl =
/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
this: equivalent to OPP_SB?
...
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {

{175, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{700, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{401, 10, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{350, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{700, 26, 1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{638, 34, 1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */


{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
Do we even support this? there is no OPP Turbo for OMAP5, we have
OPP_HIGH which needs DCC and AVS etc..
...
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{800, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{619, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{800, 26, 1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{125, 5, 1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */


{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */

};
/* dpll locked at 1200 MHz - MPU clk at 600 MHz */
Please correct this.
...
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {

{50, 0, 1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
{600, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{250, 6, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{125, 3, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{300, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{200, 8, 1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{125, 7, 1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */

Follow on question: if we are dropping ES1.0 support entirely - we
should drop it's support in id detection as well! ES1.0 and ES2.0 DPLL
configurations are different unfortunately.
...

{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */

};
static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
OPP_LOW is not supported on OMAP5 es2.0? Supported core DPLL locked frequency is
2127.36MHz?
...

{200, 2, 1, 5, 8, 4, 6, 5, -1, -1},	/* 12 MHz   */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1},	/* 13 MHz   */
{619, 12, 1, 5, 8, 4, 6, 5, -1, -1},	/* 16.8 MHz */
{125, 2, 1, 5, 8, 4, 6, 5, -1, -1},	/* 19.2 MHz */
{400, 12, 1, 5, 8, 4, 6, 5, -1, -1},	/* 26 MHz   */
{800, 26, 1, 5, 8, 4, 6, 5, -1, -1},	/* 27 MHz   */
{125, 5, 1, 5, 8, 4, 6, 5, -1, -1}	/* 38.4 MHz */


{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {

{127, 1, 1, 5, 8, 4, 6, 5, -1, -1},	/* 12 MHz   */
{762, 12, 1, 5, 8, 4, 6, 5, -1, -1},	/* 13 MHz   */
{635, 13, 1, 5, 8, 4, 6, 5, -1, -1},	/* 16.8 MHz */
{635, 15, 1, 5, 8, 4, 6, 5, -1, -1},	/* 19.2 MHz */
{381, 12, 1, 5, 8, 4, 6, 5, -1, -1},	/* 26 MHz   */
{254, 8, 1, 5, 8, 4, 6, 5, -1, -1},	/* 27 MHz   */
{496, 24, 1, 5, 8, 4, 6, 5, -1, -1}	/* 38.4 MHz */


{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params
   	core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
dumb question: what is running at 1600MHz?
...

{200, 2, 2, 5, 8, 4, 6, 5, -1, -1},	/* 12 MHz   */
{800, 12, 2, 5, 8, 4, 6, 5, -1, -1},	/* 13 MHz   */
{619, 12, 2, 5, 8, 4, 6, 5, -1, -1},	/* 16.8 MHz */
{125, 2, 2, 5, 8, 4, 6, 5, -1, -1},	/* 19.2 MHz */
{400, 12, 2, 5, 8, 4, 6, 5, -1, -1},	/* 26 MHz   */
{800, 26, 2, 5, 8, 4, 6, 5, -1, -1},	/* 27 MHz   */
{125, 5, 2, 5, 8, 4, 6, 5, -1, -1}	/* 38.4 MHz */


{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
not sure about these frequencies if verified for ES2.0
...

{64, 0, 8, 6, 12, 9, 4, 5, -1, -1},	/* 12 MHz   */
{768, 12, 8, 6, 12, 9, 4, 5, -1, -1},	/* 13 MHz   */
{320, 6, 8, 6, 12, 9, 4, 5, -1, -1},	/* 16.8 MHz */
{40, 0, 8, 6, 12, 9, 4, 5, -1, -1},	/* 19.2 MHz */
{384, 12, 8, 6, 12, 9, 4, 5, -1, -1},	/* 26 MHz   */
{256, 8, 8, 6, 12, 9, 4, 5, -1, -1},	/* 27 MHz   */
{20, 0, 8, 6, 12, 9, 4, 5, -1, -1}	/* 38.4 MHz */


{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 12 MHz   */
{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 13 MHz   */
{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 16.8 MHz */
{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 19.2 MHz */
{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 26 MHz   */
{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 27 MHz   */
{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
I might be mistaken, but i think the frequencies need an update?
...

{931, 11, -1, -1, 4, 7, -1, -1, -1, -1},	/* 12 MHz   */
{931, 12, -1, -1, 4, 7, -1, -1, -1, -1},	/* 13 MHz   */
{665, 11, -1, -1, 4, 7, -1, -1, -1, -1},	/* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1, -1, -1},	/* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1, -1, -1},	/* 26 MHz   */
{931, 26, -1, -1, 4, 7, -1, -1, -1, -1},	/* 27 MHz   */
{291, 11, -1, -1, 4, 7, -1, -1, -1, -1}		/* 38.4 MHz */


{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */

};
/* ABE M & N values with sys_clk as source */
 static const struct dpll_params
   	abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {

{49, 5, 1, 1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{68, 8, 1, 1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{29, 7, 1, 1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */


{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
/* ABE M & N values with 32K clock as source */
 static const struct dpll_params abe_dpll_params_32k_196608khz = {
We do not intend to support 32K ABE source except when doing DPLL
cascading - so this is in effect an configuration which is
un-used in any s/w line.
...

750, 0, 1, 1, -1, -1, -1, -1, -1, -1


750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1

};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {

{80, 0, 2, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
{960, 12, 2, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{320, 8, 2, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{25, 0, 2, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */


{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */

};
struct dplls omap4430_dplls_es1 = {
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index e319dc5..13ea07e 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -44,134 +44,177 @@ struct omap_sys_ctrl_regs const **ctrl =
   (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
I am not sure we'd like to do this.
...

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */


{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
again, frequency is wrong for es2.0?
...

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */


{500, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{625, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
again, frequency is wrong for es2.0?
...

{275, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */


{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
again, frequency is wrong for es2.0?
...

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */


{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
again, frequency is wrong for es2.0?
...

{200, 2, 2, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */


{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {

{275, 2, 2, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */


{275, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{550, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};
static const struct dpll_params
   		core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {

{266, 2, 2, 5, 8, 4, 62, 5, 5, 7},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{570, 8, 2, 5, 8, 4, 62, 5, 5, 7},		/* 16.8 MHz */
{665, 11, 2, 5, 8, 4, 62, 5, 5, 7},		/* 19.2 MHz */
{532, 12, 2, 5, 8, 4, 62, 5, 5, 7},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{665, 23, 2, 5, 8, 4, 62, 5, 5, 7}		/* 38.4 MHz */


{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{570, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 16.8 MHz */
{665, 11, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 19.2 MHz */
{532, 12, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{665, 23, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}		/* 38.4 MHz */

+};



+static const struct dpll_params

	core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {


{266, 2, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{443, 6, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6},		/* 16.8 MHz */
{277, 4, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6},		/* 19.2 MHz */
{368, 8, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{277, 9, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}			/* 38.4 MHz */

};
static const struct dpll_params
   		core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {

{266, 2, 4, 5, 8, 8, 62, 10, 10, 14},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{570, 8, 4, 5, 8, 8, 62, 10, 10, 14},		/* 16.8 MHz */
{665, 11, 4, 5, 8, 8, 62, 10, 10, 14},		/* 19.2 MHz */
{532, 12, 4, 8, 8, 8, 62, 10, 10, 14},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{665, 23, 4, 8, 8, 8, 62, 10, 10, 14}		/* 38.4 MHz */


{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{570, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 16.8 MHz */
{665, 11, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 19.2 MHz */
{532, 12, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{665, 23, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}		/* 38.4 MHz */

+};



+static const struct dpll_params

	core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {


{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 16.8 MHz */
{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 19.2 MHz */
{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}		/* 38.4 MHz */

};
static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {

{32, 0, 4, 3, 6, 4, -1, 2, -1, -1},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1},		/* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1},		/* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1}		/* 38.4 MHz */


{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */

+};



+static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {

{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */

};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1},	/* 16.8 MHz */
{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1},	/* 19.2 MHz */
{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1}	/* 38.4 MHz */


{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

+};



+static const struct dpll_params iva_dpll_params_2330mhz_es2[NUM_SYS_CLKS] = {

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */

};
/* ABE M & N values with sys_clk as source */
 static const struct dpll_params
   	abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {

{49, 5, 1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */


{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */

};
/* ABE M & N values with 32K clock as source */
 static const struct dpll_params abe_dpll_params_32k_196608khz = {

750, 0, 1, 1, -1, -1, -1, -1, -1, -1


750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1

};
static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {

{400, 4, 2, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */


{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */

};



spurious EOL
...
struct dplls omap5_dplls_es1 = {
   .mpu = mpu_dpll_params_800mhz,
   .core = core_dpll_params_2128mhz_ddr532,
@@ -185,6 +228,19 @@ struct dplls omap5_dplls_es1 = {
   .usb = usb_dpll_params_1920mhz
 };
+struct dplls omap5_dplls_es2 = {

.mpu = mpu_dpll_params_1100mhz,
.core = core_dpll_params_2128mhz_ddr532_es2,
.per = per_dpll_params_768mhz_es2,
.iva = iva_dpll_params_2330mhz_es2,

+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK

.abe = abe_dpll_params_sysclk_196608khz,

+#else

.abe = &abe_dpll_params_32k_196608khz,

+#endif
I strongly suggest dumping ABE sourcing from 32K clock - the code is
just a nuisance waiting to exercise an unsupported silicon feature
waiting to happen.
...

.usb = usb_dpll_params_1920mhz

+};



struct pmic_data palmas = {
   .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
   .step = 10000, /* 10 mV represented in uV */
@@ -223,6 +279,20 @@ struct vcores_data omap5432_volts = {
   .mm.pmic = &palmas,
 };
+struct vcores_data omap5430_volts_es2 = {

.mpu.value = VDD_MPU_ES2,
.mpu.addr = SMPS_REG_ADDR_12_MPU,
.mpu.pmic = &palmas,

.core.value = VDD_CORE_ES2,
.core.addr = SMPS_REG_ADDR_8_CORE,
.core.pmic = &palmas,

.mm.value = VDD_MM_ES2,
.mm.addr = SMPS_REG_ADDR_45_IVA,
.mm.pmic = &palmas,

+};



/*

Enable essential clock domains, modules and
do some additional special settings needed

@@ -454,6 +524,8 @@ void hw_data_init(void)
   case OMAP5430_ES2_0:
   case OMAP5432_ES2_0:
   *prcm = &omap5_es2_prcm;

*dplls_data = &omap5_dplls_es2;

*omap_vcores = &omap5430_volts_es2;
break;
default:


diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 15362ae..685aad5 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -208,6 +208,10 @@
 #define VDD_MM_5432	1150
 #define VDD_CORE_5432	1150
+#define VDD_MPU_ES2	1060
+#define VDD_MM_ES2	1025
+#define VDD_CORE_ES2	1040
^^^ these are meant only for OPP_NOM - considering that you have DPLLs
for OPP_SB added in, do you even expect these devices to bootup at
anything *but* OPP_NOM??
...



/* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 08395ca..8a886ec 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -426,8 +426,10 @@ struct dpll_params {
   s8 m5_h12;
   s8 m6_h13;
   s8 m7_h14;

s8 h21;
s8 h22;
s8 h23;
s8 h24;

};
struct dpll_regs {
@@ -441,9 +443,11 @@ struct dpll_regs {
   u32 cm_div_m5_h12_dpll;
   u32 cm_div_m6_h13_dpll;
   u32 cm_div_m7_h14_dpll;

u32 reserved[3];


u32 reserved[2];
u32 cm_div_h21_dpll;
u32 cm_div_h22_dpll;
u32 cm_div_h23_dpll;
u32 cm_div_h24_dpll;

};
struct dplls {
Sadly Naked-by: Nishanth Menon nm@ti.com
-- 
Regards,
Nishanth Menon

    