Based on Linux commit 6f1fe97bec349a1fd6c5a8c7c5998d759fe721d5
Currently, denali_dt.c requires a single anonymous clock, but the Denali User's Guide requires three clocks for this IP:
- clk: controller core clock
- clk_x: bus interface clock
- ecc_clk: clock at which ECC circuitry is run
This commit supports these named clocks to represent the real hardware.
For the backward compatibility, the driver still accepts a single clock just as before. The clk_x_rate is taken from the clock driver again if the named clock "clk_x" is available. This will happen only for future DT, hence the existing DT files are not affected.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
drivers/mtd/nand/raw/denali_dt.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 65a7797..f9eadb4 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -62,7 +62,7 @@ static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; - struct clk clk; + struct clk clk, clk_x, clk_ecc; struct resource res; int ret;
@@ -87,15 +87,47 @@ static int denali_dt_probe(struct udevice *dev)
denali->host = devm_ioremap(dev, res.start, resource_size(&res));
- ret = clk_get_by_index(dev, 0, &clk); + ret = clk_get_by_name(dev, "nand", &clk); + if (ret) + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret;
+ ret = clk_get_by_name(dev, "nand_x", &clk_x); + if (ret) + clk_x.dev = NULL; + + ret = clk_get_by_name(dev, "ecc", &clk_ecc); + if (ret) + clk_ecc.dev = NULL; + ret = clk_enable(&clk); if (ret) return ret;
- denali->clk_x_rate = clk_get_rate(&clk); + if (clk_x.dev) { + ret = clk_enable(&clk_x); + if (ret) + return ret; + } + + if (clk_ecc.dev) { + ret = clk_enable(&clk_ecc); + if (ret) + return ret; + } + + if (clk_x.dev) { + denali->clk_x_rate = clk_get_rate(&clk_x); + } else { + /* + * Hardcode the clock rates for the backward compatibility. + * This works for both SOCFPGA and UniPhier. + */ + dev_notice(dev, + "necessary clock is missing. default clock rates are used.\n"); + denali->clk_x_rate = 200000000; + }
return denali_init(denali); }