The A64 has 3 USB controllers and 2 USB PHYs, but a somewhat odd (actually it's wasteful, as there's no way to use the 2 PHYs and the HSIC output concurrently) muxing scheme between those: * PHY 0 is multiplexed to either MUSB (dual-role) or HCI0 * PHY 1 is dedicated to HCI1
This changeset fixes the common use-case of MUSB controlling PHY0 and HCI1 controlling PHY1. To have HCI0 control PHY0, additional work will be needed to reconcile the fact that the [eo]hci_sunxi infrastructure assumes that EHCI/OHCI controllers start at USB1.
Tested on the A64-uQ7 with MUSB (for PHY0) and HCI1 for PHY1.
Philipp Tomsich (2): sunxi (sun50i): Set CONFIG_SUNXI_USB_PHYS to 2 (the A64 has 2 PHYs) sunxi (sun50i): improved USB support for sun50i (A64)
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 12 ++++++- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 +++- arch/arm/include/asm/arch-sunxi/usb_phy.h | 2 ++ arch/arm/mach-sunxi/usb_phy.c | 48 +++++++++++++++++---------- drivers/usb/host/ehci-sunxi.c | 14 ++++++++ drivers/usb/host/ohci-sunxi.c | 8 +++++ drivers/usb/musb-new/musb_regs.h | 2 +- drivers/usb/musb-new/sunxi.c | 34 ++++++++++++++----- include/configs/sun50i.h | 2 +- 9 files changed, 98 insertions(+), 30 deletions(-)