Dear Thierry Reding,
[...]
Sure, but after you apply the bounce buffer, you can safely invalidate the whole cacheline, so align it up and be done with it.
That's what I proposed to do last time around but it was NAK'ed.
By who?
At the time I didn't ensure that the buffer was actually big enough, which is why people didn't like it (data on the stack after the DMA buffer might be invalidated as well).
Correct, thus the bounce buffer.
This is by no means Tegra specific. In fact every board that has proper cache invalidation support should expose this problem.
Yea of course, the arm926ejs had this trouble too, see the mxs MMC driver and arm926 cache.c
I suppose we could do something like this as well. If we make sure that the buffer is properly aligned and and sized, we could pass the aligned end address to invalidate_dcache_range().
Thierry
Best regards, Marek Vasut