From: Stephen Warren swarren@nvidia.com
Tegra's "APB misc" register region contains various miscellaneous registers and the Tegra pinmux registers. Some code that touches the misc registers currently uses struct pmux_tri_ctlr, which is intended to be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl, which is intended to be a definition of the miscellaneous registers. Convert all such code to use struct apb_misc_pp_ctrl, since struct pmux_tri_ctlr goes away in the next patch.
This requires adding a missing field definition to struct apb_misc_pp_ctrl, and moving the header into a more common location.
Signed-off-by: Stephen Warren swarren@nvidia.com --- V2: New patch --- arch/arm/cpu/arm720t/tegra-common/spl.c | 6 ++++-- arch/arm/cpu/tegra20-common/emc.c | 2 +- arch/arm/cpu/tegra20-common/warmboot.c | 8 +++++--- arch/arm/cpu/tegra20-common/warmboot_avp.c | 6 ++++-- arch/arm/include/asm/{arch-tegra20 => arch-tegra}/apb_misc.h | 2 ++ 5 files changed, 16 insertions(+), 8 deletions(-) rename arch/arm/include/asm/{arch-tegra20 => arch-tegra}/apb_misc.h (87%)
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c index 5171a8f907a1..3479541020b4 100644 --- a/arch/arm/cpu/arm720t/tegra-common/spl.c +++ b/arch/arm/cpu/arm720t/tegra-common/spl.c @@ -13,16 +13,18 @@ #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> +#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/board.h> #include <asm/arch/spl.h> #include "cpu.h"
void spl_board_init(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
/* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); + writel(0xC0, &apb_misc->cfg_ctl);
board_init_uart_f();
diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c index 934e39595586..ed2462ab0fa6 100644 --- a/arch/arm/cpu/tegra20-common/emc.c +++ b/arch/arm/cpu/tegra20-common/emc.c @@ -8,7 +8,7 @@ #include <fdtdec.h> #include <asm/io.h> #include <asm/arch-tegra/ap.h> -#include <asm/arch/apb_misc.h> +#include <asm/arch-tegra/apb_misc.h> #include <asm/arch/clock.h> #include <asm/arch/emc.h> #include <asm/arch/tegra.h> diff --git a/arch/arm/cpu/tegra20-common/warmboot.c b/arch/arm/cpu/tegra20-common/warmboot.c index 8beba53fc357..5fdc4bbb5007 100644 --- a/arch/arm/cpu/tegra20-common/warmboot.c +++ b/arch/arm/cpu/tegra20-common/warmboot.c @@ -15,6 +15,7 @@ #include <asm/arch/sdram_param.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/fuse.h> @@ -122,7 +123,8 @@ int warmboot_save_sdram_params(void) { u32 ram_code; struct sdram_params sdram; - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct apb_misc_gp_ctlr *gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; @@ -135,8 +137,8 @@ int warmboot_save_sdram_params(void) union fbio_spare_reg fbio_spare;
/* get ram code that is used as index to array sdram_params in BCT */ - ram_code = (readl(&pmt->pmt_strap_opt_a) >> - STRAP_OPT_A_RAM_CODE_SHIFT) & 3; + ram_code = (readl(&apb_misc->strapping_opt_a) >> + STRAP_OPT_A_RAM_CODE_SHIFT) & 3; memcpy(&sdram, (char *)((struct sdram_params *)SDRAM_PARAMS_BASE + ram_code), sizeof(sdram)); diff --git a/arch/arm/cpu/tegra20-common/warmboot_avp.c b/arch/arm/cpu/tegra20-common/warmboot_avp.c index b910f7844bb6..27ce5f480f54 100644 --- a/arch/arm/cpu/tegra20-common/warmboot_avp.c +++ b/arch/arm/cpu/tegra20-common/warmboot_avp.c @@ -12,6 +12,7 @@ #include <asm/arch/pinmux.h> #include <asm/arch/tegra.h> #include <asm/arch-tegra/ap.h> +#include <asm/arch-tegra/apb_misc.h> #include <asm/arch-tegra/clk_rst.h> #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/warmboot.h> @@ -21,7 +22,8 @@
void wb_start(void) { - struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; + struct apb_misc_pp_ctlr *apb_misc = + (struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE; struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE; struct clk_rst_ctlr *clkrst = @@ -33,7 +35,7 @@ void wb_start(void) u32 reg;
/* enable JTAG & TBE */ - writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &pmt->pmt_cfg_ctl); + writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);
/* Are we running where we're supposed to be? */ asm volatile ( diff --git a/arch/arm/include/asm/arch-tegra20/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h similarity index 87% rename from arch/arm/include/asm/arch-tegra20/apb_misc.h rename to arch/arm/include/asm/arch-tegra/apb_misc.h index f314f5acc38e..a5bc092ffdc1 100644 --- a/arch/arm/include/asm/arch-tegra20/apb_misc.h +++ b/arch/arm/include/asm/arch-tegra/apb_misc.h @@ -11,6 +11,8 @@ struct apb_misc_pp_ctlr { u32 reserved0[2]; u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ + u32 reserved1[6]; /* 0x0c .. 0x20 */ + u32 cfg_ctl; /* 0x24 */ };
/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */