On 04/06/2016 06:35 PM, Dinh Nguyen wrote:
On Wed, Mar 23, 2016 at 10:37 AM, Stefan Roese sr@denx.de wrote:
I can't really comment on the USB problem, as I've only seen this d-cache / S-bit problem with SPI NOR flash. This is because I've never really used USB on this platform intensively. But I'm nearly 100% sure, that all changes that add some delays (or debug printfs) resulting in a "working solution", either in the USB case or the SPI NOR case, are just papering over the real problem.
After a quick chat with Mark Rutland here at ELC, he alluded that there could be a problem with the PL310 interfering with the L1 DCACHE. I won't be able to try it until I get back, but perhaps somebody can test turning off the PL310?
--- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -78,7 +78,6 @@
- Cache
*/ #define CONFIG_SYS_CACHELINE_SIZE 32 -#define CONFIG_SYS_L2_PL310 #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
Dinh
If this is about disabling PL310 (L2 cache controller), then I already tried that. It did not help :(