In order to be able to run the I2C bus at 400Khz, the chip errata[1] recommends that the peripheral clock runs out of the 24MHz oscillator.
Systems running I2C from OP-TEE before Linux executes - for example to access a Secure Element [2] providing the cryptographic support - expect this clock to be configured by the bootloader [3].
[1] IMX6SLCE Rev. 5, 02/2019, ERR007805. [2] OP-TEE: support for NXP SE05X Plug and Trust (patch on the list). [3] OP-TEE: check the imx_i2c.c driver (imx6 patch on the list).
Signed-off-by: Jorge Ramirez-Ortiz jorge@foundries.io --- arch/arm/mach-imx/mx6/soc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e129286065..4c0a352574 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -26,6 +26,9 @@ #include <imx_thermal.h> #include <mmc.h>
+#define has_err007805() \ + (is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull()) + struct scu_regs { u32 ctrl; u32 config; @@ -469,7 +472,7 @@ int arch_cpu_init(void) }
/* Set perclk to source from OSC 24MHz */ - if (is_mx6sl()) + if (has_err007805()) setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK);
imx_wdog_disable_powerdown(); /* Disable PDE bit of WMCR register */