On 9 March 2016 at 08:06, George Broz brozgeo@gmail.com wrote:
On 9 March 2016 at 02:55, Marek Vasut marex@denx.de wrote:
On 03/09/2016 02:42 AM, Phil Reid wrote:
G'day George,
On 3/03/2016 10:57 PM, George Broz wrote:
On 2 March 2016 at 23:11, Phil Reid preid@electromag.com.au wrote:
On 3/03/2016 2:49 PM, George Broz wrote:
On 1 March 2016 at 19:49, Phil Reid preid@electromag.com.au wrote: > > On 2/03/2016 10:40 AM, George Broz wrote: > >> Sorry for the delayed response - got called away, but am back to this >> now. I patched >> socfpga_common.h and re-built the project. I picked up >> spl/u-boot-spl-dtb.sfp and >> u-boot-dtb.img and transferred them to the SD card with: >> >> dd if=u-boot-spl-dtb.sfp of=/dev/sdf3 bs=64k seek=0 >> dd if=u-boot-dtb.img of=/dev/sdf3 bs=64k seek=4 >> >> Tried this with both the original DT set (socfpga.dtsi, >> socfpga_cyclone.dtsi, >> socfpga_cyclone5_sockit.dts) that came with the u-boot v2016.01 >> download >> and >> also an Altera-patched DT set that I've used to boot into Linux >> numerous >> times. >> >> When I start up the board I get: >> >> U-Boot SPL 2016.01 (Mar 01 2016 - 17:28:14) >> drivers/ddr/altera/sequencer.c: Preparing to start memory calibration >> drivers/ddr/altera/sequencer.c: CALIBRATION FAILED >> drivers/ddr/altera/sequencer.c: Calibration complete >> SDRAM calibration failed. >> ### ERROR ### Please RESET the board ### >> >> I'm not a Quartus user, so I haven't done anything with the >> qts-filter.sh script you >> mentioned. Do I need to? I don't have any custom FPGA logic - it's >> just the Terasic >> board out of the box. >> >> Thanks for any help! >> > > Even without the custom FPGA logic the files generated from > qts-filter.sh > need to match your board. > Sets up PLL and SDRAM parameters. > I'm not familiar with the Terasic dev board ( I do have the altera > devkit, > but haven't used it for awhile). > I'd hope the files in the git repo are correct for your board. > Without the corresponding qsys project it's hard to be sure. > Hi Phil,
So as my next attempt, there was a Quartus/Qsys example that came with the Terasic board (specific to my Rev. of the board).
- I took the contents of the 'handoff folder', .sof, and .sopcinfo
file.
- launched an "Embedded Command Shell" from EDS 15.0 and then the BSP
editor GUI
- pointed the BSP editor to the "handoff folder", and hit "Generate"
to produce iocsr, pinmux, pll, etc. files
- applied qts-filter.sh to these files, the output of which I then
dropped into the u-boot source @ ../board/terasic/sockit/qts
- rebuilt uboot spl & image, but got a similar result:
U-Boot SPL 2016.01 (Mar 02 2016 - 22:13:31) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###
Except now it repeats four times, whereas before it only printed out once.
It that essentially the correct procedure? Is it now a matter of looking through the include files that where generated by qts-filter.sh to find a setting that is "off"?
(BTW - my first attempt was to use EDS 13.0, but that resulted in several undefined macros when it came time to compile u-boot with the qts-filter-generated code. How does one know which tool version to use?)
What does a diff of the new files show compared to the ones in uboot.
Here's two of them...
/home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h.orig
+++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/sdram_config.h
@@ -33,10 +33,10 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
@@ -46,12 +46,12 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
@@ -147,7 +147,7 @@ #define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 #define MAX_LATENCY_COUNT_WIDTH 5 #define READ_VALID_FIFO_SIZE 16 -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_DATA_MASK_WIDTH 4 #define RW_MGR_MEM_DATA_WIDTH 32
@@ -168,19 +168,20 @@
#define TRESET_CNTR2_VAL 10 /* Sequencer ac_rom_init configuration */ -const u32 ac_rom_init[] = { +const u32 ac_rom_init[] = +{ 0x20700000, 0x20780000, 0x10080431, 0x10080530, 0x10090044,
- 0x100a0008,
- 0x100a0010, 0x100b0000, 0x10380400, 0x10080449, 0x100804c8, 0x100a0024,
- 0x10090010,
- 0x10090008, 0x100b0000, 0x30780000, 0x38780000,
@@ -208,7 +209,8 @@ };
/* Sequencer inst_rom_init configuration */ -const u32 inst_rom_init[] = { +const u32 inst_rom_init[] = +{ 0x80000, 0x80680, 0x8180,
/home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h.orig
+++ /home/mcis/altera/uboot-native/u-boot-socfpga-2016.01/board/terasic/sockit/qts/pll_config.h
@@ -16,7 +16,7 @@ #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
I'm using the Quartus 15.0 tool chain at the moment. Turning on debugging in drivers/ddr/altera/sequencer.c may help.
Setting DLEVEL = 2 yields:
U-Boot SPL 2016.01 (Mar 03 2016 - 06:28:33) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration find_vfifo_failing_read:1519: vfifo 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 find_vfifo_failing_read:1519: vfifo 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1864 p: ptap=4 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1877 p/d: ptap=4 dtap=7 end=16399 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1887 found range [14003,16399] rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1895 calculate dtaps_per_ptap for tracking rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1906 backedup phase only: p=3rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1919 find passing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1927 find failing read rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase:1948 dtaps_per_ptap=21 - 8 = 13work_bgn=14003 work_end=16399 work_mid=15201 vfifo ptap delay 2496 new work_mid 225 new p 0, tmp_delay=0 new d 9, tmp_delay=225 find_dqs_en_phase: center rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (31 != 0) => 1 sdr_find_window_center:1779 center: found: ptap=0 dtap=9 rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=0 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=1 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=2 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=3 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=4 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=5 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=6 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=7 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=8 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=9 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=10 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=11 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=12 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=13 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=14 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (255 != 0) => 1 search_stop_check:2006 center(left): dtap=15 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (187 != 0) => 1 search_stop_check:2006 center(left): dtap=16 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (179 != 0) => 1 search_stop_check:2006 center(left): dtap=17 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (19 != 0) => 1 search_stop_check:2006 center(left): dtap=18 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (17 != 0) => 1 search_stop_check:2006 center(left): dtap=19 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (16 != 0) => 1 search_stop_check:2006 center(left): dtap=20 => 255 == 255 && 0rw_mgr_mem_calibrate_read_test:1457 read_test(0,ONE,0) => (0 != 0) => 0 search_stop_check:2006 center(left): dtap=21 => 255 == 255 &&à
Will try to make sense of these today...
Any insights welcome!
Any success.
You've reached the limits of my knowledge. The diff shows that there are differences in config. Failure of Memory Calibration has always been my biggest fear with hardware design.
Interesting that the 2013.01 build from the Quartus tools works. But the 2016.01 using the same qts generated files does not. Which would suggest there is something amiss in the code.
Is there similar debug statements in the 2013.01 code?
There is debug(), which you can enable by adding #define DEBUG at the beginning of drivers/ddr/altera/*.c . The other way of tracking down this bug would be to rig the writel()/readl() calls and check what values they use compared to the original altera code.
Thanks, Phil. I will see what the 2013.01 debug produces. But below is what I see if I add DEBUG to the 2016.03-rc3 code.
Marek - The marking on my DDR parts is 4NE77 D9PXV which translates to Micron part# MT41K256M16HA-125:E. I was looking at the data sheet to see if I could further manually relax some of the settings in sdram_config.h. I was also wondering what DDR parts you have on your boards. Given that your two Rev. D boards work fine, I'm beginning to think mine is defective and I'd be better off to get a new one.
Best regards, --George Broz
U-Boot SPL 2016.03-rc3 (Mar 08 2016 - 15:46:07) scc_mgr_initialize:281: Clearing SCC RFILE index 0 scc_mgr_initialize:281: Clearing SCC RFILE index 1 scc_mgr_initialize:281: Clearing SCC RFILE index 2 scc_mgr_initialize:281: Clearing SCC RFILE index 3 scc_mgr_initialize:281: Clearing SCC RFILE index 4 scc_mgr_initialize:281: Clearing SCC RFILE index 5 scc_mgr_initialize:281: Clearing SCC RFILE index 6 scc_mgr_initialize:281: Clearing SCC RFILE index 7 scc_mgr_initialize:281: Clearing SCC RFILE index 8 scc_mgr_initialize:281: Clearing SCC RFILE index 9 scc_mgr_initialize:281: Clearing SCC RFILE index 10 scc_mgr_initialize:281: Clearing SCC RFILE index 11 scc_mgr_initialize:281: Clearing SCC RFILE index 12 scc_mgr_initialize:281: Clearing SCC RFILE index 13 scc_mgr_initialize:281: Clearing SCC RFILE index 14 scc_mgr_initialize:281: Clearing SCC RFILE index 15 drivers/ddr/altera/sequencer.c: Preparing to start memory calibration DDR3 FULL_RATE ranks=1 cs/dimm=1 dq/dqs=8,8 vg/dqs=1,1 dqs=5,5 dq=40 dm=5 ptap_delay=312 dtap_delay=25 dtap_dqsen_delay=25, dll=8max values: en_p=7 dqdqs_p=0 en_d=31 dqs_in_d=31 io_in_d=31 io_out1_d=31 io_out2_d=0 dqs_in_reserve=4 dqs_out_reserve=6 scc_mgr_set_hhp_extras:477 Setting HHP Extras scc_mgr_set_hhp_extras:480 Done Setting HHP Extras rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=0 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(0,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=0 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=0 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-5 (index=3) vfifo_center: new mid_min=-5 new_dqs=9 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=9 mid_min=-5 get_window_mid_index:2288 vfifo_center: *mid_min=2 (index=6) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=0 (index=3) vfifo_center: new mid_min=0 new_dqs=9 vfifo_center: start_dqs=9 start_dqs_en=-1 new_dqs=9 mid_min=0 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=1 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(1,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=1 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=1 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-4 (index=3) vfifo_center: new mid_min=-4 new_dqs=8 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=8 mid_min=-4 get_window_mid_index:2288 vfifo_center: *mid_min=2 (index=2) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=-1 (index=3) vfifo_center: new mid_min=-1 new_dqs=9 vfifo_center: start_dqs=8 start_dqs_en=-1 new_dqs=9 mid_min=-1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=2 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(2,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=2 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=2 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-3 (index=3) vfifo_center: new mid_min=-3 new_dqs=7 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=7 mid_min=-3 get_window_mid_index:2288 vfifo_center: *mid_min=2 (index=2) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=-1 (index=7) vfifo_center: new mid_min=-1 new_dqs=8 vfifo_center: start_dqs=7 start_dqs_en=-1 new_dqs=8 mid_min=-1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=3 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(3,ALL) => (255 == 255) => 0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=0 p=0 d=0 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=1 p=1 d=4 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=2 p=2 d=8 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=3 p=3 d=12 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=4 p=4 d=16 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=5 p=5 d=20 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=6 p=6 d=24 rw_mgr_mem_calibrate_dqs_enable_calibration:2590: g=3 r=0 i=7 p=7 d=28 rw_mgr_mem_calibrate_dqs_enable_calibration:2607: g=3 found=1; Reseting delay chain to zero get_window_mid_index:2288 vfifo_center: *mid_min=-4 (index=7) vfifo_center: new mid_min=-4 new_dqs=8 vfifo_center: start_dqs=4 start_dqs_en=-1 new_dqs=8 mid_min=-4 get_window_mid_index:2288 vfifo_center: *mid_min=1 (index=2) rw_mgr_mem_calibrate_writes_center:3005 write_center: start_dqs=6 new_dqs=6 mid_min=0 get_window_mid_index:2288 vfifo_center: *mid_min=0 (index=3) vfifo_center: new mid_min=0 new_dqs=8 vfifo_center: start_dqs=8 start_dqs_en=-1 new_dqs=8 mid_min=0 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 2) DQS: 2 > 0; adding 2 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 2) DQS: 2 > 0; adding 2 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 4) DQS: 4 > 0; adding 4 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 4) DQS: 4 > 0; adding 4 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 6) DQS: 6 > 0; adding 6 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 6) DQS: 6 > 0; adding 6 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 8) DQS: 8 > 0; adding 8 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 8) DQS: 8 > 0; adding 8 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 10) DQS: 10 > 0; adding 10 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 10) DQS: 10 > 0; adding 10 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 scc_mgr_apply_group_all_out_delay_add:691 (4, 12) DQS: 12 > 0; adding 12 to OUT1 scc_mgr_apply_group_all_out_delay_add:705 (4, 12) DQS: 12 > 0; adding 12 to OUT1 rw_mgr_mem_calibrate_guaranteed_write:2534 guaranteed write: g=4 p=0 rw_mgr_mem_calibrate_read_test_patterns:1290 test_load_patterns(4,ALL) => (170 == 255) => -5 rw_mgr_mem_calibrate_guaranteed_write:2554 Guaranteed read test failed: g=4 p=0 drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###
I'll try and find time to build with the 2016.01 debug statements here and send you a log for comparison.
-- Best regards, Marek Vasut
Hello again -
So under the assumption my SoCKit h/w was broken, I bought a new board. They are back ordered on SoCKit boards, so I got a DE0-Nano-SoC instead.
I build the v2016.03 (release) version of u-boot-with-spl.sfp.
I power-up the (brand new) board and get:
U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###
U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION FAILED drivers/ddr/altera/sequencer.c: Calibration complete SDRAM calibration failed. ### ERROR ### Please RESET the board ###
U-Boot SPL 2016.03 (Mar 15 2016 - 14:52:42) drivers/ddr/altera/sequencer.c: Preparing to start memory calibration drivers/ddr/altera/sequencer.c: CALIBRATION PASSED drivers/ddr/altera/sequencer.c: Calibration complete Trying to boot from MMC
U-Boot 2016.03 (Mar 15 2016 - 14:52:42 -0700)
CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A4 or SX/C4, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) Watchdog enabled I2C: ready DRAM: 1 GiB MMC: dwmmc0@ff704000: 0 In: serial Out: serial Err: serial Model: Terasic DE0-Nano(Atlas) Net: Error: ethernet@ff702000 address not set. No ethernet found. Hit any key to stop autoboot: 0 =>
And this is a good case... usually it doesn't succeed after the fourth try and I have to cycle power 4 or 5 times before I get lucky.
If I do get lucky and then try to see a USB storage device, then I get:
=> => usb start starting USB... USB0: Core Release: 2.93a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... 1 USB Device(s) found =>
(Every time)
The version of u-boot SPL that ships with the board: U-Boot SPL 2013.01.01 (Dec 29 2014 - 15:29:15)
boots every time and has limited USB capability as it can see some USB sticks, but not others.
Anyway - brand new board - same old symptoms.
Is it perhaps a toolchain problem?? I'm using:
Thread model: posix gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 4.9-2014.11)
COLLECT_GCC=arm-poky-linux-gnueabi-gcc COLLECT_LTO_WRAPPER=/opt/poky/1.7.1/sysroots/x86_64-pokysdk-linux/usr/libexec/arm-poky-linux-gnueabi/gcc/arm-poky-linux-gnueabi/4.9.3/lto-wrapper < snip >
Any advice greatly appreciated.
Regards, --George Broz