Padding or number of line required for instruction, address and data is pre-defined as per the selected read commond.
Configure LUT based on the selected read command under flag SPI_XFER_BEGIN.
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com --- drivers/spi/fsl_qspi.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 7ec222a..bdaec44 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -52,7 +52,12 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_PP 0x02 /* Page program (up to 256 bytes) */ #define QSPI_CMD_RDSR 0x05 /* Read status register */ #define QSPI_CMD_WREN 0x06 /* Write enable */ +#define QSPI_CMD_SLOW_READ 0x03 /* Read data bytes (low frequency) */ #define QSPI_CMD_FAST_READ 0x0b /* Read data bytes (high frequency) */ +#define QSPI_CMD_DUAL_OUTPUT_FAST_READ 0x3b +#define QSPI_CMD_DUAL_IO_FAST_READ 0xbb +#define QSPI_CMD_QUAD_OUTPUT_FAST_READ 0x6b +#define QSPI_CMD_QUAD_IO_FAST_READ 0xeb #define QSPI_CMD_BE_4K 0x20 /* 4K erase */ #define QSPI_CMD_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define QSPI_CMD_SE 0xd8 /* Sector erase (usually 64KiB) */ @@ -71,7 +76,12 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD_WRAR 0x71 /* Write any device register */
/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */ -#define QSPI_CMD_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */ +#define QSPI_CMD_SLOW_READ_4B 0x13 +#define QSPI_CMD_FAST_READ_4B 0x0c +#define QSPI_CMD_DUAL_OUTPUT_FAST_READ_4B 0x3c +#define QSPI_CMD_DUAL_IO_FAST_READ_4B 0xbc +#define QSPI_CMD_QUAD_OUTPUT_FAST_READ_4B 0x6c +#define QSPI_CMD_QUAD_IO_FAST_READ_4B 0xec #define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */ #define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
@@ -762,10 +772,51 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen, { u32 bytes = DIV_ROUND_UP(bitlen, 8); static u32 wr_sfaddr; - u32 txbuf; + u32 txbuf, mode = priv->mode;
WATCHDOG_RESET();
+ if (dout && (flags & SPI_XFER_BEGIN)) { + switch (*(u8 *)dout) { + case QSPI_CMD_SLOW_READ: + case QSPI_CMD_SLOW_READ_4B: + case QSPI_CMD_FAST_READ: + case QSPI_CMD_FAST_READ_4B: + case QSPI_CMD_PP: + case QSPI_CMD_PP_4B: + /* TODO: 1_1_1 Padding */ + break; + + case QSPI_CMD_DUAL_OUTPUT_FAST_READ: + case QSPI_CMD_DUAL_OUTPUT_FAST_READ_4B: + if (mode & SPI_RX_DUAL) { + /* TODO: 1_1_2 Padding */ + } + break; + + case QSPI_CMD_DUAL_IO_FAST_READ: + case QSPI_CMD_DUAL_IO_FAST_READ_4B: + if (mode & SPI_RX_DUAL) { + /* TODO: 1_2_2 Padding */ + } + break; + + case QSPI_CMD_QUAD_OUTPUT_FAST_READ: + case QSPI_CMD_QUAD_OUTPUT_FAST_READ_4B: + if (mode & SPI_RX_QUAD) { + /* TODO: 1_1_4 Padding */ + } + break; + + case QSPI_CMD_QUAD_IO_FAST_READ: + case QSPI_CMD_QUAD_IO_FAST_READ_4B: + if (mode & SPI_RX_QUAD) { + /* TODO: 1_4_4 Padding */ + } + break; + } + } + if (dout) { if (flags & SPI_XFER_BEGIN) { priv->cur_seqid = *(u8 *)dout;