On Fri, Jan 20, 2023 at 9:18 AM Sumit Garg sumit.garg@linaro.org wrote:
The GMAC controller on QCS404 SoC (support added by upcoming patch) fails to work with maximum tx/rx_fifo_sz supported by the hardware (16K). So allow platforms to override FIFO size using corresponding DT node properties.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
drivers/net/dwc_eth_qos.c | 19 +++++++++++++------ drivers/net/dwc_eth_qos.h | 1 + 2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 753a912607..65b8556be2 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -852,12 +852,19 @@ static int eqos_start(struct udevice *dev) rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
/** r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.* r/tqs is encoded as (n / 256) - 1.*/tqs = (128 << tx_fifo_sz) / 256 - 1;rqs = (128 << rx_fifo_sz) / 256 - 1;
/* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */tx_fifo_sz = 128 << tx_fifo_sz;rx_fifo_sz = 128 << rx_fifo_sz;/* Allow platform to override TX/RX fifo size */if (eqos->tx_fifo_sz)tx_fifo_sz = eqos->tx_fifo_sz;if (eqos->rx_fifo_sz)rx_fifo_sz = eqos->rx_fifo_sz;/* r/tqs is encoded as (n / 256) - 1 */tqs = tx_fifo_sz / 256 - 1;rqs = rx_fifo_sz / 256 - 1; clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 8fccd6f057..466a792de7 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -276,6 +276,7 @@ struct eqos_priv { bool started; bool reg_access_ok; bool clk_ck_enabled;
unsigned int tx_fifo_sz, rx_fifo_sz;};
void eqos_inval_desc_generic(void *desc);
2.34.1
Reviewed-by: Ramon Fried rfried.dev@gmail.com