On Wed, 2007-07-18 at 07:50, David Saada wrote:
I've got the MPC8568MDS board. When I try to compile the latest version of U-boot for this board and burn it onto its flash, the boot process gets stuck right after the RAM initialization sequence (it prints the DDR+SDRAM size, but doesn't continue).
If you use 1.93 or above version of MPC8568MDS, you need to modify some settings for DDR initialization in spd_sdram.c. In specific, you need to modify clk_adjust and cpo value, you can take the follow patch as reference. This patch has not been submitted yet but included in the BSP already.
--- cpu/mpc85xx/spd_sdram.c | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 3777f49..ba255f8 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -645,13 +645,10 @@ spd_sdram(void) */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { - if (effective_data_rate == 266 || effective_data_rate == 333) { + if (effective_data_rate <= 333) { cpo = 0x7; /* READ_LAT + 5/4 */ - } else if (effective_data_rate == 400) { - cpo = 0x9; /* READ_LAT + 7/4 */ } else { - /* Pure speculation */ - cpo = 0xb; + cpo = 0x9; /* READ_LAT + 7/4 */ } }
@@ -858,7 +855,12 @@ spd_sdram(void) if (spd.mem_type == SPD_MEMTYPE_DDR) clk_adjust = 0x6; else +#ifdef CONFIG_MPC8568 + /* Empirally setting clk_adjust */ + clk_adjust = 0x6; +#else clk_adjust = 0x7; +#endif
ddr->sdram_clk_cntl = (0 | 0x80000000