On Saturday 25 December 2021 21:15:13 Pierre Bourdon wrote:
On Sat, Dec 25, 2021 at 9:01 PM Pali Rohár pali@kernel.org wrote:
Perfect, problem solved. Anyway, I would be really interested in your kwb cfg file as it is probably image layout which reveal this issue.
It's a very basic configuration, inspired from board/mikrotik/crs3xx-98dx3236/kwbimage.cfg.in but for NAND booting:
VERSION 1 BOOT_FROM nand NAND_BLKSZ 00020000 NAND_BADBLK_LOCATION 00
Probably it is because of NAND alignment. Other Armada boards use SPI for booting...
BINARY ./board/qnap/qsw-98dx3236/binary.0 0000005b 00000068
I can't upload the actual KWB images I'm using because this is using a DDR3 training blob extracted from my vendor's build and I'm unsure about the licensing.
Could you ask vendor about it? Armada DDR3 training code is for a longer time also under GPL and BSD license.
Marvell U-Boot for 32-bit Armada boards is available on Marvell github and latest version in u-boot-2013.01-armada-18.06 branch: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/tree/u-boot-2013...
Source code for BINARY header is in tools/marvell/bin_hdr directory: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/tree/u-boot-2013...
IIRC those prestera switches are marked as Armada "msys" architecture.