Add a device tree node for the Allwinner R40/V40 GMAC gigabit ethernet interface. The R40 SoC does not use the syscon register for GMAC settings. The gigabit ethernet interface can only be routed to a fixed set of pins. Updated to match the Linux kernel's device tree.
Signed-off-by: Lothar Felten lothar.felten@gmail.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com Reviewed-by: Jagan Teki jagan@openedev.com Tested-by: Jagan Teki jagan@openedev.com
--- Changelog: new in v2 v2 -> v3 omit syscon node for R40 v3 -> v4 remove phy-mode from gmac node v4 -> v5 match Linux device tree suggested by Chen-Yu Tsai v5 -> v6 none --- arch/arm/dts/sun8i-r40.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 0aa76a2f10..2cdfb54282 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -161,6 +161,19 @@ #interrupt-cells = <3>; #gpio-cells = <3>;
+ gmac_rgmii_pins: gmac-rgmii-pins { + pins = "PA0", "PA1", "PA2", "PA3", + "PA4", "PA5", "PA6", "PA7", + "PA8", "PA10", "PA11", "PA12", + "PA13", "PA15", "PA16"; + function = "gmac"; + /* + * data lines in RGMII mode use DDR mode + * and need a higher signal drive strength + */ + drive-strength = <40>; + }; + i2c0_pins: i2c0_pins { pins = "PB0", "PB1"; function = "i2c0"; @@ -202,6 +215,27 @@ #size-cells = <0>; };
+ gmac: ethernet@1c50000 { + compatible = "allwinner,sun8i-r40-gmac"; + syscon = <&ccu>; + reg = <0x01c50000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_GMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_GMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + gmac_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>,