This patch adds support for Samsung TRATS board
Signed-off-by: HeungJun, Kim riverful.kim@samsung.com Signed-off-by: Kyungmin Park kyungmin.park@samsung.com --- MAINTAINERS | 4 + board/samsung/trats/Makefile | 44 ++++ board/samsung/trats/lowlevel_init.S | 284 +++++++++++++++++++++ board/samsung/trats/trats.c | 246 +++++++++++++++++++ board/samsung/trats/trats_setup.h | 460 +++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/trats.h | 222 +++++++++++++++++ 7 files changed, 1261 insertions(+), 0 deletions(-) create mode 100644 board/samsung/trats/Makefile create mode 100644 board/samsung/trats/lowlevel_init.S create mode 100644 board/samsung/trats/trats.c create mode 100644 board/samsung/trats/trats_setup.h create mode 100644 include/configs/trats.h
diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10..c856c59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -700,6 +700,10 @@ Minkyu Kang mk7.kang@samsung.com s5p_goni ARM ARMV7 (S5PC110 SoC) s5pc210_universal ARM ARMV7 (EXYNOS4210 SoC)
+Heungjun Kim riverful.kim@samsung.com + + trats ARM ARMV7 (EXYNOS4210 SoC) + Chander Kashyap k.chander@samsung.com
origen ARM ARMV7 (EXYNOS4210 SoC) diff --git a/board/samsung/trats/Makefile b/board/samsung/trats/Makefile new file mode 100644 index 0000000..5a31a7b --- /dev/null +++ b/board/samsung/trats/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2010 Samsung Electronics +# Heungjun Kim riverful.kim@samsung.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License version 2 as +# published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := trats.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(SOBJS) $(OBJS) + $(call cmd_link_o_target, $(SOBJS) $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/samsung/trats/lowlevel_init.S b/board/samsung/trats/lowlevel_init.S new file mode 100644 index 0000000..7b8e15b --- /dev/null +++ b/board/samsung/trats/lowlevel_init.S @@ -0,0 +1,284 @@ +/* + * Lowlevel setup for TRATS board based on EXYNOS4210 + * + * Copyright (C) 2010 Samsung Electronics + * Heungjun Kim riverful.kim@samsung.com + * Kyungmin Park kyungmin.park@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include "trats_setup.h" + +/* + * Register usages: + * + * r5 has zero always + * r7 has GPIO part1 base 0x11400000 + * r6 has GPIO part2 base 0x11000000 + */ + + .globl lowlevel_init +lowlevel_init: + push {lr} + + /* r5 has always zero */ + mov r5, #0 + ldr r7, =EXYNOS4_GPIO_PART1_BASE + ldr r6, =EXYNOS4_GPIO_PART2_BASE + + /* + * PMIC manual reset + * nPOWER: XEINT_23: GPX2[7] + */ + ldr r1, =EXYNOS4_GPIO_X2_CON_VAL + str r1, [r6, #EXYNOS4_GPIO_X2_CON_OFFSET] + ldr r1, =EXYNOS4_GPIO_X2_DAT_VAL + str r1, [r6, #EXYNOS4_GPIO_X2_DAT_OFFSET] + + /* init system clock */ + bl system_clock_init + + /* Disable Watchdog */ + ldr r0, =EXYNOS4_WATCHDOG_BASE + str r5, [r0] + + /* UART */ + bl uart_asm_init + + /* PMU init */ + bl system_power_init + + pop {pc} + nop + nop + nop + +/* + * uart_asm_init: Initialize UART's pins + */ +uart_asm_init: + /* + * setup UART0-UART4 GPIOs (part1) + * GPA1CON[3] = I2C_3_SCL (3) + * GPA1CON[2] = I2C_3_SDA (3) + */ + mov r0, r7 + ldr r1, =EXYNOS4_GPIO_A0_CON_VAL + str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET] + ldr r1, =EXYNOS4_GPIO_A1_CON_VAL + str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET] + + /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ + ldr r1, =EXYNOS4_GPIO_Y4_CON_VAL + str r1, [r6, #EXYNOS4_GPIO_Y4_CON_OFFSET] + ldr r1, =EXYNOS4_GPIO_Y4_PUD_VAL + str r1, [r6, #EXYNOS4_GPIO_Y4_PUD_OFFSET] + ldr r1, =EXYNOS4_GPIO_Y4_DAT_VAL + str r1, [r6, #EXYNOS4_GPIO_Y4_DAT_OFFSET] + + mov pc, lr + nop + nop + nop + +system_clock_init: + ldr r0, =EXYNOS4_CLOCK_BASE + + /* APLL(1), MPLL(1), CORE(0), HPM(0) */ + ldr r1, =CLK_SRC_CPU_VAL + ldr r2, =CLK_SRC_CPU_OFFSET + str r1, [r0, r2] + + /* wait ?us */ + mov r1, #0x10000 +1: subs r1, r1, #1 + bne 1b + + /* + * CLK_SRC_TOP0 + * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL + * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL + */ + ldr r1, =CLK_SRC_TOP0_VAL + ldr r2, =CLK_SRC_TOP0_OFFSET + str r1, [r0, r2] + /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ + ldr r1, =CLK_SRC_FSYS_VAL + ldr r2, =CLK_SRC_FSYS_OFFSET + str r1, [r0, r2] + /* UART[0:5] */ + ldr r1, =CLK_SRC_PERIL0_VAL + ldr r2, =CLK_SRC_PERIL0_OFFSET + str r1, [r0, r2] + /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */ + ldr r1, =CLK_DIV_CPU0_VAL + ldr r2, =CLK_DIV_CPU0_OFFSET + str r1, [r0, r2] + /* CPU1: COPY, HPM */ + ldr r1, =CLK_DIV_CPU1_VAL + ldr r2, =CLK_DIV_CPU1_OFFSET + str r1, [r0, r2] + /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */ + ldr r1, =CLK_DIV_DMC0_VAL + ldr r2, =CLK_DIV_DMC0_OFFSET + str r1, [r0, r2] + /* DMC1: PWI, DVSEM, DPM */ + ldr r1, =CLK_DIV_DMC1_VAL + ldr r2, =CLK_DIV_DMC1_OFFSET + str r1, [r0, r2] + /* LEFTBUS: GDL, GPL */ + ldr r1, =CLK_DIV_LEFTBUS_VAL + ldr r2, =CLK_DIV_LEFTBUS_OFFSET + str r1, [r0, r2] + /* RIGHHTBUS: GDR, GPR */ + ldr r1, =CLK_DIV_RIGHTBUS_VAL + ldr r2, =CLK_DIV_RIGHTBUS_OFFSET + str r1, [r0, r2] + + /* + * CLK_DIV_TOP + * ACLK_200, ACLK_100, ACLK_160, ACLK_133, + */ + ldr r1, =CLK_DIV_TOP_VAL + ldr r2, =CLK_DIV_TOP_OFFSET + str r1, [r0, r2] + /* MMC[0:1] */ + ldr r1, =CLK_DIV_FSYS1_VAL + ldr r2, =CLK_DIV_FSYS1_OFFSET + str r1, [r0, r2] + /* MMC[2:3] */ + ldr r1, =CLK_DIV_FSYS2_VAL + ldr r2, =CLK_DIV_FSYS2_OFFSET + str r1, [r0, r2] + /* MMC4 */ + ldr r1, =CLK_DIV_FSYS3_VAL + ldr r2, =CLK_DIV_FSYS3_OFFSET + str r1, [r0, r2] + /* UART[0:5] */ + ldr r1, =CLK_DIV_PERIL0_VAL + ldr r2, =CLK_DIV_PERIL0_OFFSET + str r1, [r0, r2] + + /* PLL Setting */ + ldr r1, =PLL_LOCKTIME + ldr r2, =APLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r2, =MPLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r2, =EPLL_LOCK_OFFSET + str r1, [r0, r2] + ldr r2, =VPLL_LOCK_OFFSET + str r1, [r0, r2] + + /* APLL */ + ldr r1, =APLL_CON1_VAL + ldr r2, =APLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =APLL_CON0_VAL + ldr r2, =APLL_CON0_OFFSET + str r1, [r0, r2] + /* MPLL */ + ldr r1, =MPLL_CON1_VAL + ldr r2, =MPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =MPLL_CON0_VAL + ldr r2, =MPLL_CON0_OFFSET + str r1, [r0, r2] + /* EPLL */ + ldr r1, =EPLL_CON1_VAL + ldr r2, =EPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =EPLL_CON0_VAL + ldr r2, =EPLL_CON0_OFFSET + str r1, [r0, r2] + /* VPLL */ + ldr r1, =VPLL_CON1_VAL + ldr r2, =VPLL_CON1_OFFSET + str r1, [r0, r2] + ldr r1, =VPLL_CON0_VAL + ldr r2, =VPLL_CON0_OFFSET + str r1, [r0, r2] + + /* Clock Gating */ + ldr r1, =CLK_GATE_IP_CAM_VAL + ldr r2, =CLK_GATE_IP_CAM_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_VP_VAL + ldr r2, =CLK_GATE_IP_VP_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_MFC_VAL + ldr r2, =CLK_GATE_IP_MFC_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_G3D_VAL + ldr r2, =CLK_GATE_IP_G3D_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_IMAGE_VAL + ldr r2, =CLK_GATE_IP_IMAGE_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_LCD0_VAL + ldr r2, =CLK_GATE_IP_LCD0_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_LCD1_VAL + ldr r2, =CLK_GATE_IP_LCD1_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_FSYS_VAL + ldr r2, =CLK_GATE_IP_FSYS_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_GPS_VAL + ldr r2, =CLK_GATE_IP_GPS_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_PERIL_VAL + ldr r2, =CLK_GATE_IP_PERIL_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_IP_PERIR_VAL + ldr r2, =CLK_GATE_IP_PERIR_OFFSET + str r1, [r0, r2] + ldr r1, =CLK_GATE_BLOCK_VAL + ldr r2, =CLK_GATE_BLOCK_OFFSET + str r1, [r0, r2] + mov pc, lr + nop + nop + nop + +system_power_init: + ldr r0, =EXYNOS4_POWER_BASE + + /* PS HOLD */ + ldr r1, =EXYNOS4_PS_HOLD_CON_VAL + ldr r2, =EXYNOS4_PS_HOLD_CON_OFFSET + str r1, [r0, r2] + + /* Power Down */ + add r2, r0, #POWER_DOWN_OFFSET + str r5, [r2, #POWER_TV_CONFIGURATION_OFFSET] + str r5, [r2, #POWER_MFC_CONFIGURATION_OFFSET] + str r5, [r2, #POWER_G3D_CONFIGURATION_OFFSET] + str r5, [r2, #POWER_LCD_CONFIGURATION_OFFSET] + str r5, [r2, #POWER_GPS_CONFIGURATION_OFFSET] + + mov pc, lr + nop + nop + nop + diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c new file mode 100644 index 0000000..7639d60 --- /dev/null +++ b/board/samsung/trats/trats.c @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Heungjun Kim riverful.kim@samsung.com + * Kyungmin Park kyungmin.park@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <pmic.h> +#include <usb/s3c_udc.h> +#include <asm/arch/cpu.h> +#include <max8998_pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct exynos4_gpio_part1 *gpio1; +struct exynos4_gpio_part2 *gpio2; +unsigned int board_rev; + +u32 get_board_rev(void) +{ + return board_rev; +} + +static void check_hw_revision(void); + +int board_init(void) +{ + gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE; + gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE; + + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + check_hw_revision(); + printf("HW Revision:\t0x%x\n", board_rev); + +#if defined(CONFIG_PMIC) + pmic_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + +static unsigned int get_hw_revision(void) +{ + int hwrev = 0; + int i; + + /* hw_rev[3:0] == GPE1[3:0] */ + for (i = 0; i < 4; i++) { + s5p_gpio_cfg_pin(&gpio1->e1, i, GPIO_INPUT); + s5p_gpio_set_pull(&gpio1->e1, i, GPIO_PULL_NONE); + } + + udelay(1); + + for (i = 0; i < 4; i++) + hwrev |= (s5p_gpio_get_value(&gpio1->e1, i) << i); + + debug("hwrev 0x%x\n", hwrev); + + return hwrev; +} + +static void check_hw_revision(void) +{ + int hwrev; + + hwrev = get_hw_revision(); + + board_rev |= hwrev; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + puts("Board:\tTRATS\n"); + return 0; +} +#endif + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + int i, err; + + /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ + s5p_gpio_direction_output(&gpio2->k0, 2, 1); + s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); + + /* + * eMMC GPIO: + * SDR 8-bit@48MHz at MMC0 + * GPK0[0] SD_0_CLK(2) + * GPK0[1] SD_0_CMD(2) + * GPK0[2] SD_0_CDn -> Not used + * GPK0[3:6] SD_0_DATA[0:3](2) + * GPK1[3:6] SD_0_DATA[0:3](3) + * + * DDR 4-bit@26MHz at MMC4 + * GPK0[0] SD_4_CLK(3) + * GPK0[1] SD_4_CMD(3) + * GPK0[2] SD_4_CDn -> Not used + * GPK0[3:6] SD_4_DATA[0:3](3) + * GPK1[3:6] SD_4_DATA[4:7](4) + */ + for (i = 0; i < 7; i++) { + if (i == 2) + continue; + /* GPK0[0:6] special function 2 */ + s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2); + /* GPK0[0:6] pull disable */ + s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); + /* GPK0[0:6] drv 4x */ + s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); + } + + for (i = 3; i < 7; i++) { + /* GPK1[3:6] special function 3 */ + s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3); + /* GPK1[3:6] pull disable */ + s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); + /* GPK1[3:6] drv 4x */ + s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); + } + + /* + * MMC device init + * mmc0 : eMMC (8-bit buswidth) + * mmc2 : SD card (4-bit buswidth) + */ + err = s5p_mmc_init(0, 8); + + /* T-flash detect */ + s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); + s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); + + /* + * Check the T-flash detect pin + * GPX3[4] T-flash detect pin + */ + if (!s5p_gpio_get_value(&gpio2->x3, 4)) { + /* + * SD card GPIO: + * GPK2[0] SD_2_CLK(2) + * GPK2[1] SD_2_CMD(2) + * GPK2[2] SD_2_CDn -> Not used + * GPK2[3:6] SD_2_DATA[0:3](2) + */ + for (i = 0; i < 7; i++) { + if (i == 2) + continue; + /* GPK2[0:6] special function 2 */ + s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2); + /* GPK2[0:6] pull disable */ + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + /* GPK2[0:6] drv 4x */ + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + } + err = s5p_mmc_init(2, 4); + } + + return err; + +} +#endif + +#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{ + int ret = 0; + struct pmic *p = get_pmic(); + + if (pmic_probe(p)) + return -1; + + if (on) { + ret |= pmic_set_output(p, + MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, + MAX8998_SAFEOUT1, LDO_ON); + ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, + MAX8998_LDO3, LDO_ON); + ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, + MAX8998_LDO8, LDO_ON); + + } else { + ret |= pmic_set_output(p, MAX8998_REG_ONOFF2, + MAX8998_LDO8, LDO_OFF); + ret |= pmic_set_output(p, MAX8998_REG_ONOFF1, + MAX8998_LDO3, LDO_OFF); + ret |= pmic_set_output(p, + MAX8998_REG_BUCK_ACTIVE_DISCHARGE3, + MAX8998_SAFEOUT1, LDO_OFF); + } + + if (ret) { + puts("MAX8998 LDO setting error!\n"); + return -1; + } + + return 0; +} + +struct s3c_plat_otg_data s5pc210_otg_data = { + .phy_control = s5pc210_phy_control, + .regs_phy = EXYNOS4_USBPHY_BASE, + .regs_otg = EXYNOS4_USBOTG_BASE, + .usb_phy_ctrl = EXYNOS4_USBPHY_CONTROL, + .usb_flags = PHY0_SLEEP, +}; +#endif diff --git a/board/samsung/trats/trats_setup.h b/board/samsung/trats/trats_setup.h new file mode 100644 index 0000000..adf037b --- /dev/null +++ b/board/samsung/trats/trats_setup.h @@ -0,0 +1,460 @@ +/* + * Machine Specific Values for TRATS board based on EXYNOS4210 + * + * Copyright (C) 2010 Samsung Electronics + * Heungjun Kim riverful.kim@samsung.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TRATS_SETUP_H +#define _TRATS_SETUP_H + +#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> + +/* Offsets of clock registers (sources and dividers) */ +#define CLK_SRC_CPU_OFFSET 0x14200 +#define CLK_DIV_CPU0_OFFSET 0x14500 +#define CLK_DIV_CPU1_OFFSET 0x14504 + +#define CLK_DIV_DMC0_OFFSET 0x10500 +#define CLK_DIV_DMC1_OFFSET 0x10504 + +#define CLK_SRC_TOP0_OFFSET 0xC210 +#define CLK_DIV_TOP_OFFSET 0xC510 + +#define CLK_DIV_LEFTBUS_OFFSET 0x4500 +#define CLK_DIV_RIGHTBUS_OFFSET 0x8500 + +#define CLK_SRC_FSYS_OFFSET 0xC240 +#define CLK_DIV_FSYS1_OFFSET 0xC544 +#define CLK_DIV_FSYS2_OFFSET 0xC548 +#define CLK_DIV_FSYS3_OFFSET 0xC54C + +#define CLK_SRC_PERIL0_OFFSET 0xC250 +#define CLK_DIV_PERIL0_OFFSET 0xC550 + +#define APLL_LOCK_OFFSET 0x14000 +#define MPLL_LOCK_OFFSET 0x14008 +#define APLL_CON0_OFFSET 0x14100 +#define APLL_CON1_OFFSET 0x14104 +#define MPLL_CON0_OFFSET 0x14108 +#define MPLL_CON1_OFFSET 0x1410C + +#define EPLL_LOCK_OFFSET 0xC010 +#define VPLL_LOCK_OFFSET 0xC020 +#define EPLL_CON0_OFFSET 0xC110 +#define EPLL_CON1_OFFSET 0xC114 +#define VPLL_CON0_OFFSET 0xC120 +#define VPLL_CON1_OFFSET 0xC124 + +#define CLK_GATE_IP_CAM_OFFSET 0xC920 +#define CLK_GATE_IP_VP_OFFSET 0xC924 +#define CLK_GATE_IP_MFC_OFFSET 0xC928 +#define CLK_GATE_IP_G3D_OFFSET 0xC92C +#define CLK_GATE_IP_IMAGE_OFFSET 0xC930 +#define CLK_GATE_IP_LCD0_OFFSET 0xC934 +#define CLK_GATE_IP_LCD1_OFFSET 0xC938 +#define CLK_GATE_IP_FSYS_OFFSET 0xC940 +#define CLK_GATE_IP_GPS_OFFSET 0xC94C +#define CLK_GATE_IP_PERIL_OFFSET 0xC950 +#define CLK_GATE_IP_PERIR_OFFSET 0xC960 +#define CLK_GATE_BLOCK_OFFSET 0xC970 + +#define PS_HOLD_CONTROL_OFFSET 0x330C + +#define POWER_DOWN_OFFSET 0x3000 +#define POWER_TV_CONFIGURATION_OFFSET 0xC20 +#define POWER_MFC_CONFIGURATION_OFFSET 0xC40 +#define POWER_G3D_CONFIGURATION_OFFSET 0xC60 +#define POWER_LCD_CONFIGURATION_OFFSET 0xCA0 +#define POWER_GPS_CONFIGURATION_OFFSET 0xCE0 + +/* GPIO Offsets for UART: GPIO Contol Register */ +#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00 +#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20 +#define EXYNOS4_GPIO_Y4_CON_OFFSET 0x1A0 +#define EXYNOS4_GPIO_Y4_DAT_OFFSET 0x1A4 +#define EXYNOS4_GPIO_Y4_PUD_OFFSET 0x1A8 + +/* GPIO Offsets for PMIC: GPIO Contol & Data Register */ +#define EXYNOS4_GPIO_X2_CON_OFFSET 0xC40 +#define EXYNOS4_GPIO_X2_DAT_OFFSET 0xC44 + +/* GPIO Offsets for PS_HOLD: GPIO Control Register */ +#define EXYNOS4_PS_HOLD_CON_OFFSET 0x330C + +/* PMIC Reset pin: nPOWER - GPX2[7] */ +#define EXYNOS4_GPIO_X2_CON_VAL 0x10000000 +#define EXYNOS4_GPIO_X2_DAT_VAL 0x80 + +/* UART_SEL: Pull enabled */ +#define EXYNOS4_GPIO_Y4_CON_VAL 0x10000000 +#define EXYNOS4_GPIO_Y4_PUD_VAL 0xC000 +#define EXYNOS4_GPIO_Y4_DAT_VAL 0x80 + +/* PS_HOLD: Data Hight, Output En */ +#define EXYNOS4_PS_HOLD_CON_VAL 0x300 + +/* Power Down value */ +#define POWER_DOWN_VAL 0x3000 + +/* CLK_SRC_CPU */ +#define MUX_HPM_SEL_MOUTAPLL 0x0 +#define MUX_HPM_SEL_SCLKMPLL 0x1 +#define MUX_CORE_SEL_MOUTAPLL 0x0 +#define MUX_CORE_SEL_SCLKMPLL 0x1 +#define MUX_MPLL_SEL_FILPLL 0x0 +#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1 +#define MUX_APLL_SEL_FILPLL 0x0 +#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1 +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \ + | (MUX_CORE_SEL_MOUTAPLL << 16) \ + | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\ + | (MUX_APLL_SEL_MOUTMPLLFOUT << 0)) + +/* CLK_DIV_CPU0 */ +#define APLL_RATIO 0x0 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x3 +#define PERIPH_RATIO 0x3 +#define COREM1_RATIO 0x7 +#define COREM0_RATIO 0x3 +#define CORE_RATIO 0x0 +#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20) \ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO << 12) \ + | (COREM1_RATIO << 8) \ + | (COREM0_RATIO << 4) \ + | (CORE_RATIO << 0)) + +/* CLK_DIV_CPU1 */ +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x3 +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) + +/* CLK_DIV_DMC0 */ +#define CORE_TIMERS_RATIO 0x1 +#define COPY2_RATIO 0x3 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x1 +#define DMC_RATIO 0x1 +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#define ACP_RATIO 0x3 +#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ + | (COPY2_RATIO << 24) \ + | (DMCP_RATIO << 20) \ + | (DMCD_RATIO << 16) \ + | (DMC_RATIO << 12) \ + | (DPHY_RATIO << 8) \ + | (ACP_PCLK_RATIO << 4) \ + | (ACP_RATIO << 0)) + +/* CLK_DIV_DMC1 */ +#define DPM_RATIO 0x1 +#define DVSEM_RATIO 0x1 +#define PWI_RATIO 0x1 +#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ + | (DVSEM_RATIO << 16) \ + | (PWI_RATIO << 8)) + +/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_SEL_ACLK_133 0x0 +#define MUX_ONENAND_SEL_ACLK_160 0x1 +#define MUX_ACLK_133_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_133_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_160_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_160_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_100_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_100_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_200_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_200_SEL_SCLKAPLL 0x1 +#define MUX_VPLL_SEL_FINPLL 0x0 +#define MUX_VPLL_SEL_FOUTVPLL 0x1 +#define MUX_EPLL_SEL_FINPLL 0x0 +#define MUX_EPLL_SEL_FOUTEPLL 0x1 +#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0 +#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1 +#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_160 << 28) \ + | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \ + | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \ + | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \ + | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \ + | (MUX_VPLL_SEL_FOUTVPLL << 8) \ + | (MUX_EPLL_SEL_FOUTEPLL << 4) \ + | (MUX_ONENAND_1_SEL_MOUTONENAND << 0)) + +/* CLK_DIV_TOP */ +#define ONENAND_RATIO 0x0 +#define ACLK_133_RATIO 0x5 +#define ACLK_160_RATIO 0x4 +#define ACLK_100_RATIO 0x7 +#define ACLK_200_RATIO 0x3 +#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ + | (ACLK_133_RATIO << 12)\ + | (ACLK_160_RATIO << 8) \ + | (ACLK_100_RATIO << 4) \ + | (ACLK_200_RATIO << 0)) + +/* CLK_DIV_LEFTBUS */ +#define GPL_RATIO 0x1 +#define GDL_RATIO 0x3 +#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) + +/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO 0x1 +#define GDR_RATIO 0x3 +#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) + +/* CLK_SRS_FSYS: 6 = SCLKMPLL */ +#define SATA_SEL_SCLKMPLL 0 +#define SATA_SEL_SCLKAPLL 1 + +#define MMC_SEL_XXTI 0 +#define MMC_SEL_XUSBXTI 1 +#define MMC_SEL_SCLK_HDMI24M 2 +#define MMC_SEL_SCLK_USBPHY0 3 +#define MMC_SEL_SCLK_USBPHY1 4 +#define MMC_SEL_SCLK_HDMIPHY 5 +#define MMC_SEL_SCLKMPLL 6 +#define MMC_SEL_SCLKEPLL 7 +#define MMC_SEL_SCLKVPLL 8 + +#define MMCC0_SEL MMC_SEL_SCLKMPLL +#define MMCC1_SEL MMC_SEL_SCLKMPLL +#define MMCC2_SEL MMC_SEL_SCLKMPLL +#define MMCC3_SEL MMC_SEL_SCLKMPLL +#define MMCC4_SEL MMC_SEL_SCLKMPLL +#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \ + | (MMCC4_SEL << 16) \ + | (MMCC3_SEL << 12) \ + | (MMCC2_SEL << 8) \ + | (MMCC1_SEL << 4) \ + | (MMCC0_SEL << 0)) + +/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */ +/* CLK_DIV_FSYS1: 800(MPLL) / (15 + 1) */ +#define MMC0_RATIO 0xF +#define MMC0_PRE_RATIO 0x0 +#define MMC1_RATIO 0xF +#define MMC1_PRE_RATIO 0x0 +#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ + | (MMC1_RATIO << 16) \ + | (MMC0_PRE_RATIO << 8) \ + | (MMC0_RATIO << 0)) + +/* CLK_DIV_FSYS2: 800(MPLL) / (15 + 1) */ +#define MMC2_RATIO 0xF +#define MMC2_PRE_RATIO 0x0 +#define MMC3_RATIO 0xF +#define MMC3_PRE_RATIO 0x0 +#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ + | (MMC3_RATIO << 16) \ + | (MMC2_PRE_RATIO << 8) \ + | (MMC2_RATIO << 0)) + +/* CLK_DIV_FSYS3: 800(MPLL) / (15 + 1) */ +#define MMC4_RATIO 0xF +#define MMC4_PRE_RATIO 0x0 +#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ + | (MMC4_RATIO << 0)) + +/* CLK_SRC_PERIL0 */ +#define UART_SEL_XXTI 0 +#define UART_SEL_XUSBXTI 1 +#define UART_SEL_SCLK_HDMI24M 2 +#define UART_SEL_SCLK_USBPHY0 3 +#define UART_SEL_SCLK_USBPHY1 4 +#define UART_SEL_SCLK_HDMIPHY 5 +#define UART_SEL_SCLKMPLL 6 +#define UART_SEL_SCLKEPLL 7 +#define UART_SEL_SCLKVPLL 8 + +#define UART0_SEL UART_SEL_SCLKMPLL +#define UART1_SEL UART_SEL_SCLKMPLL +#define UART2_SEL UART_SEL_SCLKMPLL +#define UART3_SEL UART_SEL_SCLKMPLL +#define UART4_SEL UART_SEL_SCLKMPLL +#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \ + | (UART3_SEL << 12) \ + | (UART2_SEL << 8) \ + | (UART1_SEL << 4) \ + | (UART0_SEL << 0)) + +/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */ +/* CLK_DIV_PERIL0 */ +#define UART0_RATIO 7 +#define UART1_RATIO 7 +#define UART2_RATIO 7 +#define UART3_RATIO 4 +#define UART4_RATIO 7 +#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ + | (UART3_RATIO << 12) \ + | (UART2_RATIO << 8) \ + | (UART1_RATIO << 4) \ + | (UART0_RATIO << 0)) + +/* Required period to generate a stable clock output */ +/* PLL_LOCK_TIME */ +#define PLL_LOCKTIME 0x1C20 + +/* PLL Values */ +#define DISABLE 0 +#define ENABLE 1 +#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ + | (mdiv << 16) \ + | (pdiv << 8) \ + | (sdiv << 0)) + +/* APLL_CON0: 800MHz */ +#define APLL_MDIV 0xC8 +#define APLL_PDIV 0x6 +#define APLL_SDIV 0x1 +#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV) + +/* APLL_CON1 */ +#define APLL_AFC_ENB 0x1 +#define APLL_AFC 0x1C +#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0)) + +/* MPLL_CON0: 800MHz */ +#define MPLL_MDIV 0xC8 +#define MPLL_PDIV 0x6 +#define MPLL_SDIV 0x1 +#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) + +/* MPLL_CON1 */ +#define MPLL_AFC_ENB 0x1 +#define MPLL_AFC 0x1C +#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) + +/* EPLL_CON0: 96MHz */ +#define EPLL_MDIV 0x30 +#define EPLL_PDIV 0x3 +#define EPLL_SDIV 0x2 +#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) + +/* EPLL_CON1 */ +#define EPLL_K 0x0 +#define EPLL_CON1_VAL (EPLL_K >> 0) + +/* VPLL_CON0: 108MHz */ +#define VPLL_MDIV 0x35 +#define VPLL_PDIV 0x3 +#define VPLL_SDIV 0x2 +#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) + +/* VPLL_CON1 */ +#define VPLL_SSCG_EN DISABLE +#define VPLL_SEL_PF_DN_SPREAD 0x0 +#define VPLL_MRR 0x11 +#define VPLL_MFR 0x0 +#define VPLL_K 0x400 +#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\ + | (VPLL_SEL_PF_DN_SPREAD << 29) \ + | (VPLL_MRR << 24) \ + | (VPLL_MFR << 16) \ + | (VPLL_K << 0)) + +/* + * GATE CAM: SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001 + * Turn off all + */ +#define CLK_GATE_IP_CAM_VAL 0xFFF80000 + +/* GATE VP: Turn off all */ +#define CLK_GATE_IP_VP_VAL 0xFFFFFFC0 + +/* GATE MFC: Turn off all */ +#define CLK_GATE_IP_MFC_VAL 0xFFFFFFE0 + +/* GATE G3D: Turn off all */ +#define CLK_GATE_IP_G3D_VAL 0xFFFFFFFC + +/* GATE IMAGE: Turn off all */ +#define CLK_GATE_IP_IMAGE_VAL 0xFFFFFC00 + +/* GATE LCD0: DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */ +#define CLK_GATE_IP_LCD0_VAL 0xFFFFFFF1 + +/* GATE LCD1: Turn off all */ +#define CLK_GATE_IP_LCD1_VAL 0xFFFFFFC0 + +/* + * GATE FSYS + * SMMUPCIE[18], NFCON[16] : 1111 1010 + * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000 + * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011 + */ +#define CLK_GATE_IP_FSYS_VAL 0xFFFAB8A3 + +/* GATE GPS: Turn off all */ +#define CLK_GATE_IP_GPS_VAL 0xFFFFFFFC + +/* + * GATE PERI Left + * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001 + * I2C2[8] : 1111 1110 + */ +#define CLK_GATE_IP_PERIL_VAL 0xF1FFFEFF + +/* + * GATE PERI Right + * KEYIF[16] : 1111 1110 + */ +#define CLK_GATE_IP_PERIR_VAL 0xFFFEFFFF + +/* GATE Block: LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */ +#define CLK_GATE_BLOCK_VAL 0xFFFFFFD1 + +/* + * UART GPIO_A0/GPIO_A1 Control Register Value + * 0x2: UART Function + * GPA1CON[3] = I2C_3_SCL (3), GPA1CON[2] = I2C_3_SDA (3) + */ +#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222 +#define EXYNOS4_GPIO_A1_CON_VAL 0x223322 + +/* ULCON: UART Line Control Value 8N1 */ +#define WORD_LEN_5_BIT 0x00 +#define WORD_LEN_6_BIT 0x01 +#define WORD_LEN_7_BIT 0x02 +#define WORD_LEN_8_BIT 0x03 + +#define STOP_BIT_1 0x00 +#define STOP_BIT_2 0x01 + +#define NO_PARITY 0x00 +#define ODD_PARITY 0x4 +#define EVEN_PARITY 0x5 +#define FORCED_PARITY_CHECK_AS_1 0x6 +#define FORCED_PARITY_CHECK_AS_0 0x7 + +#define INFRAMODE_NORMAL 0x00 +#define INFRAMODE_INFRARED 0x01 + +#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \ + | (NO_PARITY << 3) \ + | (STOP_BIT_1 << 2) \ + | (WORD_LEN_8_BIT << 0)) + +#endif diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..53ebb77 100644 --- a/boards.cfg +++ b/boards.cfg @@ -218,6 +218,7 @@ smdkc100 arm armv7 smdkc100 samsung origen arm armv7 origen samsung exynos s5pc210_universal arm armv7 universal_c210 samsung exynos smdkv310 arm armv7 smdkv310 samsung exynos +trats arm armv7 trats samsung exynos harmony arm armv7 harmony nvidia tegra2 seaboard arm armv7 seaboard nvidia tegra2 ventana arm armv7 ventana nvidia tegra2 diff --git a/include/configs/trats.h b/include/configs/trats.h new file mode 100644 index 0000000..4ed9ac4 --- /dev/null +++ b/include/configs/trats.h @@ -0,0 +1,222 @@ +/* + * Copyright (C) 2010 Samsung Electronics + * Heungjun Kim riverful.kim@samsung.com + * + * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ +#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */ +#define CONFIG_TRATS 1 /* working with TRATS */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_L2CACHE_OFF 1 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x44800000 + +/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */ +#define CONFIG_SYS_CLK_FREQ_C210 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_EDITING + +/* MACH_TYPE_TRATS macro will be removed once added to mach-types */ +#define MACH_TYPE_TRATS 3928 +#define CONFIG_MACH_TYPE MACH_TYPE_TRATS + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* select serial console configuration */ +#define CONFIG_SERIAL_MULTI 1 +#define CONFIG_SERIAL2 1 /* use SERIAL 2 */ +#define CONFIG_BAUDRATE 115200 + +/* MMC */ +#define CONFIG_GENERIC_MMC 1 +#define CONFIG_MMC 1 +#define CONFIG_S5P_MMC 1 + +/* PWM */ +#define CONFIG_PWM 1 + +/* It should define before config_cmd_default.h */ +#define CONFIG_SYS_NO_FLASH 1 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MMC + +#define CONFIG_BOOTDELAY 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define MBRPARTS_DEFAULT "20M(permanent)"\ + ",20M(boot)"\ + ",1G(system)"\ + ",100M(swap)"\ + ",-(UMS)\0" + +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run mmcboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +#define CONFIG_BOOTBLOCK "10" + +#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootk=" \ + "run loaduimage; bootm 0x40007FC0\0" \ + "updatemmc=" \ + "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ + "mmc boot 0 1 1 0\0" \ + "updatebackup=" \ + "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ + "mmc boot 0 1 1 0\0" \ + "updatebootb=" \ + "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ + "lpj=lpj=3981312\0" \ + "nfsboot=" \ + "set bootargs root=/dev/nfs rw " \ + "nfsroot=${nfsroot},nolock,tcp " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ + "; run bootk\0" \ + "ramfsboot=" \ + "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ + "${console} ${meminfo} " \ + "initrd=0x43000000,8M ramdisk=8192\0" \ + "mmcboot=" \ + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ + "run loaduimage; bootm 0x40007FC0\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ + "verify=n\0" \ + "rootfstype=ext4\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "mbrparts=" MBRPARTS_DEFAULT \ + "meminfo=crashkernel=32M@0x50000000\0" \ + "nfsroot=/nfsroot/arm\0" \ + "bootblock=" CONFIG_BOOTBLOCK "\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ + "mmcdev=0\0" \ + "mmcbootpart=2\0" \ + "mmcrootpart=3\0" \ + "opts=always_resume=1" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "TRATS # " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Stack sizes */ +#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */ + +/* TRATS has 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ +#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */ +#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ +#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */ + +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */ + +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#include <asm/arch/gpio.h> +/* + * I2C Settings + */ +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) + +#define CONFIG_SOFT_I2C +#define CONFIG_SOFT_I2C_READ_REPEATED_START +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 7 + +#define CONFIG_PMIC +#define CONFIG_PMIC_I2C +#define CONFIG_PMIC_MAX8998 + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED + +#endif /* __CONFIG_H */