I have 2 AMCC yucca boards, one Rev A silicon, and one Rev B silicon.
Using commit 2721a68a9ea91f1e494649ce68b2577261f578e2, (8th March, 2007 "Small AMCC Katmai 440SPe update"), DDR2 works fine (with the original Micron DIMMS, anyway). But the next commit, 2f5df47351910a2936c7741cf111855829200943 (8th March, "Update AMCC Yucca 440SPe eval board support") which adds support for initialising SDRAM using the I2C prom, always reports:
"ERROR: Cannot determine a common read delay for the DIMM(s) installed."
This happens on both the Rev A board, and the Rev B board. Oddly enough, on our own custom board which is very similar to the Yucca, it passes fine.
Has anyone ever seen this before?
A full dump of the boot log (with some extra debug enabled) follows.
Regards, Dale
U-Boot 1.2.0 (Jul 23 2007 - 20:30:52)
CPU: AMCC PowerPC 440SPe Rev. A at 533.333 MHz (PLB=133, OPB=66, EBC=66 MHz) RAID 6 support I2C boot EEPROM enabled Bootstrap Option D - Boot ROM Location I2C (Addr 0x50) Internal PCI arbiter enabled 32 kB I-Cache 32 kB D-Cache Board: Yucca - AMCC 440SPe Evaluation Board I2C: ready DRAM: spd_read(0x53) returned 128 spd_read(0x53) returned 8 DIMM slot 0: populated
spd_read(0x52) returned 128 spd_read(0x52) returned 8 DIMM slot 1: populated DIMM slot 0: DDR2 SDRAM detected DIMM slot 1: DDR2 SDRAM detected nb of dimm 2 nb of rank 4 CAS latency = 40 Write recovery = 5 ERROR: Cannot determine a common read delay for the DIMM(s) installed. DQS_calibration_process[2630] ERROR : ### ERROR ### Please RESET the board ###