Hi Niek,
On 11/29/23 18:58, niek.nooijens@omron.com wrote:
Hi Fabio
I'm using the socfpga_cyclone5 with the designwire_spi driver. I added the TPM to the devicetree as so: &spi0 { status = "okay"; num-cs = <2>; mram0@0 { compatible = "spi-dev"; reg = <0>; spi-max-frequency = <1000000>; }; tpm@1 { // slm9670 - U144 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <1>; spi-max-frequency = <1000000>; }; };
The DW SPI device does not support holding the CS low between separate reads/writes. The easiest fix is to use a GPIO CS. However, you can also rewrite the SPI slave driver to use mem_ops, which will ensure that the CS stays high for a transaction. However, this may not be possible for all slaves. For more info, have a look at commit fec7bf0460d ("spi: dw: Add mem_ops").
--Sean
NIek ________________________________ 差出人: Fabio Estevam festevam@gmail.com 送信日時: 2023年11月29日 22:17 宛先: Niek Nooijens / OC-IAB PBD-C DEVEL 1-1 niek.nooijens@omron.com CC: u-boot@lists.denx.de u-boot@lists.denx.de 件名: Re: TPM SPI issue
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Hi Niek,
On Wed, Nov 29, 2023 at 9:51 AM niek.nooijens@omron.com niek.nooijens@omron.com wrote:
Hi there
I have the same issue as here: https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fcommunity....https://community.infineon.com/t5/OPTIGA-TPM/I-MX8-TPM-SLB9670-SPI-Com-Error/td-p/472533
apparently the CS is released in between responses. Can you help me solve this?
Which SoC are you using?
In case you are using drivers/spi/mxc_spi.c, there was a commit in the kernel driver that allowed to put the CS line in low when idle:
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.kernel...https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.3&id=6a983ff5102ff0d859df05ca3f5cf2f6a17c0fad