CONFIG_SYS_DDR_BASE is specific to mpc83xx an is always set to the same value as CONFIG_SYS_SDRAM_BASE. Just use CONFIG_SYS_SDRAM_BASE instead.
Signed-off-by: Mario Six mario.six@gdsys.cc
---
v1 -> v2: New in v2
--- board/esd/vme8349/vme8349.c | 2 +- board/freescale/mpc8323erdb/mpc8323erdb.c | 2 +- board/freescale/mpc832xemds/mpc832xemds.c | 2 +- board/freescale/mpc8349emds/mpc8349emds.c | 2 +- board/freescale/mpc8349itx/mpc8349itx.c | 2 +- board/ids/ids8313/ids8313.c | 2 +- board/keymile/km83xx/km83xx.c | 4 ++-- board/sbc8349/sbc8349.c | 2 +- board/tqc/tqm834x/tqm834x.c | 6 +++--- board/ve8313/ve8313.c | 2 +- include/configs/MPC8308RDB.h | 5 ++--- include/configs/MPC8313ERDB_NAND.h | 5 ++--- include/configs/MPC8313ERDB_NOR.h | 5 ++--- include/configs/MPC8315ERDB.h | 5 ++--- include/configs/MPC8323ERDB.h | 5 ++--- include/configs/MPC832XEMDS.h | 5 ++--- include/configs/MPC8349EMDS.h | 5 ++--- include/configs/MPC8349EMDS_SDRAM.h | 5 ++--- include/configs/MPC8349ITX.h | 5 ++--- include/configs/MPC837XEMDS.h | 5 ++--- include/configs/MPC837XERDB.h | 5 ++--- include/configs/TQM834x.h | 5 ++--- include/configs/caddy2.h | 5 ++--- include/configs/hrcon.h | 5 ++--- include/configs/ids8313.h | 5 ++--- include/configs/kmcoge5ne.h | 5 ++--- include/configs/kmeter1.h | 5 ++--- include/configs/kmopti2.h | 5 ++--- include/configs/kmsupx5.h | 5 ++--- include/configs/kmtegr1.h | 5 ++--- include/configs/kmtepr2.h | 5 ++--- include/configs/kmvect1.h | 5 ++--- include/configs/mpc8308_p1m.h | 5 ++--- include/configs/sbc8349.h | 5 ++--- include/configs/strider.h | 5 ++--- include/configs/suvd3.h | 5 ++--- include/configs/tuge1.h | 5 ++--- include/configs/tuxx1.h | 5 ++--- include/configs/ve8313.h | 5 ++--- include/configs/vme8349.h | 5 ++--- scripts/config_whitelist.txt | 1 - 41 files changed, 73 insertions(+), 104 deletions(-)
diff --git a/board/esd/vme8349/vme8349.c b/board/esd/vme8349/vme8349.c index a46d0b6da63..4c220fa8e13 100644 --- a/board/esd/vme8349/vme8349.c +++ b/board/esd/vme8349/vme8349.c @@ -38,7 +38,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main memory */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = spd_sdram();
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 772688186b5..2dc6d7f5f5f 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -79,7 +79,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c index 869538feb92..61b95c601e6 100644 --- a/board/freescale/mpc832xemds/mpc832xemds.c +++ b/board/freescale/mpc832xemds/mpc832xemds.c @@ -98,7 +98,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
msize = fixed_sdram();
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 4ec0af4d1c5..1c34f1dc38c 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -56,7 +56,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) #ifndef CONFIG_SYS_FSL_DDR2 msize = spd_sdram() * 1024 * 1024; diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index 62bcf235711..aaaea7ce89f 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -132,7 +132,7 @@ int dram_init(void) return -ENXIO;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #ifdef CONFIG_SPD_EEPROM msize = spd_sdram(); #else diff --git a/board/ids/ids8313/ids8313.c b/board/ids/ids8313/ids8313.c index a411d4e7f6f..f2ccabc3162 100644 --- a/board/ids/ids8313/ids8313.c +++ b/board/ids/ids8313/ids8313.c @@ -96,7 +96,7 @@ int fixed_sdram(unsigned long config) setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); /* now check the real size */ disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); #endif return msize; diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 1fd6f919014..880ce67fa6c 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -311,7 +311,7 @@ static int fixed_sdram(void)
msize = CONFIG_SYS_DDR_SIZE << 20; disable_addr_trans(); - msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans(); msize /= (1024 * 1024); if (CONFIG_SYS_DDR_SIZE != msize) { @@ -338,7 +338,7 @@ int dram_init(void) return -ENXIO;
out_be32(&im->sysconf.ddrlaw[0].bar, - CONFIG_SYS_DDR_BASE & LAWBAR_BAR); + CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR); msize = fixed_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c index b8ba29ac6da..5584b3d1796 100644 --- a/board/sbc8349/sbc8349.c +++ b/board/sbc8349/sbc8349.c @@ -45,7 +45,7 @@ int dram_init(void) return -1;
/* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index c75251e132c..04941b26be4 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -72,13 +72,13 @@ int dram_init(void) int cs;
/* during size detection, set up the max DDRLAW size */ - im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE; im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
/* set CS bounds to maximum size */ for(cs = 0; cs < 4; ++cs) { set_cs_bounds(cs, - CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), + CONFIG_SYS_SDRAM_BASE + (cs * DDR_MAX_SIZE_PER_CS), DDR_MAX_SIZE_PER_CS);
set_cs_config(cs, INITIAL_CS_CONFIG); @@ -102,7 +102,7 @@ int dram_init(void) debug("\nDetecting Bank%d\n", cs);
bank_size = get_ddr_bank_size(cs, - (long *)(CONFIG_SYS_DDR_BASE + size)); + (long *)(CONFIG_SYS_SDRAM_BASE + size)); size += bank_size;
debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index f0fc1fe3b31..609585bc653 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -80,7 +80,7 @@ static long fixed_sdram(void)
/* now check the real size */ disable_addr_trans (); - msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize); + msize = get_ram_size (CONFIG_SYS_SDRAM_BASE, msize); enable_addr_trans (); #endif
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index e625f8709cb..d9361fd8a03 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -36,9 +36,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 08c5b56da71..08c83996c73 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -86,9 +86,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 337c5b391d3..083eac0ce3f 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -58,9 +58,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b49022b916d..c5a229deb4c 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -34,9 +34,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 497c60bcdaa..3e6febfc9d3 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -23,9 +23,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
#undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 520f01f177d..4b3f70c916c 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -20,9 +20,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
#undef CONFIG_SPD_EEPROM diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 20433445248..1a96be0895c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -52,9 +52,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 70fc29e8ade..311f87b5b3c 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -52,9 +52,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 6f040a3d6dc..bb3bcfcc448 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -142,9 +142,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x2000 diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 5f0050a97d5..e34a36cadd8 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -35,9 +35,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ef23d004085..33d4ced92f7 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -58,9 +58,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 8171f8531ba..53fac4d675a 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -24,9 +24,8 @@ * DDR Setup */ /* DDR is system memory*/ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define DDR_CASLAT_25 /* CASLAT set to 2.5 */ #undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index a0642aef112..f14e5faafa6 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -51,9 +51,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 0919bb544d0..ae3fcfd3d79 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -24,9 +24,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index ddc268977e1..1d56d24c15a 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -51,9 +51,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index bee7f586ddd..fc60b01d38c 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -43,11 +43,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 2c56f00a18b..644cc0ff098 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -28,11 +28,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 4ac428b3651..bcdce27566f 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 5d52c9051a9..94cbcf58fe5 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index e7dd05076a2..c8e5d303b10 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -55,11 +55,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index e2b6a5990bc..2673ecbb905 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index fe4496e9bc9..4ad30453f68 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -47,11 +47,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index aca4a655e03..8836b70b762 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -39,9 +39,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6bad6511339..709387ecf79 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -46,9 +46,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/include/configs/strider.h b/include/configs/strider.h index 69e22fb141e..c01531c3ca2 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -24,9 +24,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | DDRCDR_PZ_LOZ \ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 11a15c60ee5..72ed00fce75 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -45,11 +45,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index 76e1749cd1e..005d114510d 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index c7be955645c..62e9db4e1b8 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -48,11 +48,10 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 8b20bfd1003..cd6c686b890 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -34,9 +34,8 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE
/* * Manually set up DDR parameters, as this board does not diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d50a5263a70..14a84fabc97 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -51,9 +51,8 @@ */ #undef CONFIG_DDR_32BIT
-#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4fdd7927b1b..c15dcfa7f52 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -2309,7 +2309,6 @@ CONFIG_SYS_DDRCDR_VALUE CONFIG_SYS_DDRD CONFIG_SYS_DDRTC CONFIG_SYS_DDRUA -CONFIG_SYS_DDR_BASE CONFIG_SYS_DDR_BLOCK1_SIZE CONFIG_SYS_DDR_BLOCK2_BASE CONFIG_SYS_DDR_CDR_1