This series adds support for Cadence QSPI controller present on K2G SoC.
The first patch extends AHB address to 32 bit as K2G has 32 bit AHB address. Second patch to enable QUAD mode based on DT data instead of relying on config option. And last to patches add DT node and add configs to enable the driver.
Depends on [1] to enable SPI driver model support on K2G and [2] to support different bus frequencies for two different SPI controllers present on K2G EVM.
[1]https://www.mail-archive.com/u-boot@lists.denx.de/msg217952.html [2]https://www.mail-archive.com/u-boot@lists.denx.de/msg217964.html
Rebased on top of v2016.07-rc3
Vignesh R (4): spi: cadence_qspi_apb: Support 32 bit AHB address spi: cadence_quadspi: Enable QUAD mode based on DT data ARM: dts: K2G: Add support for QSPI controller defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller
arch/arm/dts/k2g-evm.dts | 45 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/k2g.dtsi | 14 +++++++++++++ configs/k2g_evm_defconfig | 2 ++ drivers/spi/cadence_qspi.c | 3 ++- drivers/spi/cadence_qspi.h | 2 +- drivers/spi/cadence_qspi_apb.c | 15 +++++++------- include/configs/k2g_evm.h | 6 ++++++ 7 files changed, 77 insertions(+), 10 deletions(-)