From: Yinbo Zhu yinbo.zhu@nxp.com
This patch is to set sdhc clock for ppc
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- Change in v3: (struct fsl_esdhc *)(addr) => (struct fsl_esdhc *)addr
drivers/mmc/fsl_esdhc.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9e34557d16..88a5b0c46d 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1428,7 +1428,9 @@ void fdt_fixup_esdhc(void *blob, bd_t *bd) #endif
#if CONFIG_IS_ENABLED(DM_MMC) +#ifndef CONFIG_PPC #include <asm/arch/clock.h> +#endif __weak void init_clk_usdhc(u32 index) { } @@ -1560,7 +1562,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->sdhc_clk = clk_get_rate(&priv->per_clk); } else { +#ifndef CONFIG_PPC priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq); +#else + priv->sdhc_clk = gd->arch.sdhc_clk; +#endif if (priv->sdhc_clk <= 0) { dev_err(dev, "Unable to get clk for %s\n", dev->name); return -EINVAL;