
4 Oct
2008
4 Oct
'08
1:35 a.m.
Dear Haiying Wang,
In message 1223051524-22415-1-git-send-email-Haiying.Wang@freescale.com you wrote:
Fix some bugs:
- Correctly set intlv_ctl in cs_config.
- Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
- Set base_address and total memory for each ddr controller in memory controller interleaving mode.
Can you please (re-) submit your patches with a valid subject?
Please keep in mind that the subject is used as the tile line of the commit message, so it is essential.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
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