Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.
Signed-off-by: York Sun yorksun@freescale.com --- README | 5 +++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 ++ arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 7 +++++++ arch/powerpc/cpu/mpc85xx/fdt.c | 6 +++++- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 5 +++++ 5 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/README b/README index cd0336c..353d016 100644 --- a/README +++ b/README @@ -418,6 +418,11 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround.
+ CONFIG_SYS_FSL_DDR_EMU + + Specify emulator support for DDR. Some DDR features such as deskew training + are not available. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 4067f05..fd19d99 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -545,8 +545,10 @@ skip_l2:
enable_cpc();
+#ifndef CONFIG_SYS_FSL_NO_SERDES /* needs to be in ram since code uses global static vars */ fsl_serdes_init(); +#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871 if (IS_SVR_REV(svr, 1, 0)) { diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c index c5b4720..3e7a564 100644 --- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c +++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c @@ -123,10 +123,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); +#ifndef CONFIG_SYS_FSL_DDR_EMU + /* + * Skip these two registers if running on emulator + * because emulator doesn't have skew between bytes. + */ + if (regs->ddr_wrlvl_cntl_2) out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); if (regs->ddr_wrlvl_cntl_3) out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); +#endif
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 288f7b2..8072235 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -620,8 +620,12 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob);
+#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV +#define CONFIG_FSL_TBCLK_EXTRA_DIV 1 +#endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, - "timebase-frequency", get_tbclk(), 1); + "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV, + 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "bus-frequency", bd->bi_busfreq, 1); get_sys_info(&sysinfo); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index 26c42f7..8c95cad 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1641,5 +1641,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_sdram_rcw(ddr, popts, common_dimm);
+#ifdef CONFIG_SYS_FSL_DDR_EMU + /* disble DDR training for emulator */ + ddr->debug[2] = 0x00000400; + ddr->debug[4] = 0xff800000; +#endif return check_fsl_memctl_config_regs(ddr); }