4 Jan
2023
4 Jan
'23
8:19 p.m.
On 12/11/22 21:50, Yanhong Wang wrote:
Add initial u-boot device tree for the JH7110 RISC-V SoC.
Signed-off-by: Yanhong Wang yanhong.wang@starfivetech.com
arch/riscv/dts/jh7110-u-boot.dtsi | 86 +++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 arch/riscv/dts/jh7110-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi new file mode 100644 index 0000000000..243237e83a --- /dev/null +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/*
- Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
+#include <dt-bindings/reset/starfive-jh7110.h>
+/ {
- cpus: cpus {
u-boot,dm-spl;cpu0: cpu@0 {u-boot,dm-spl;status = "okay";cpu0_intc: interrupt-controller {u-boot,dm-spl;};};cpu1: cpu@1 {u-boot,dm-spl;cpu1_intc: interrupt-controller {u-boot,dm-spl;};};cpu2: cpu@2 {u-boot,dm-spl;cpu2_intc: interrupt-controller {u-boot,dm-spl;};};cpu3: cpu@3 {u-boot,dm-spl;cpu3_intc: interrupt-controller {u-boot,dm-spl;};};cpu4: cpu@4 {u-boot,dm-spl;cpu4_intc: interrupt-controller {u-boot,dm-spl;};};
Use the S76_0/U74_1/etc references you defined earlier.
- };
- soc {
u-boot,dm-spl;clint: clint@2000000 {u-boot,dm-spl;};dmc: dmc@15700000 {u-boot,dm-spl;compatible = "starfive,jh7110-dmc";reg = <0x0 0x15700000 0x0 0x10000>,<0x0 0x13000000 0x0 0x10000>;resets = <&syscrg JH7110_SYSRST_DDR_AXI>,<&syscrg JH7110_SYSRST_DDR_OSC>,<&syscrg JH7110_SYSRST_DDR_APB>;reset-names = "axi", "osc", "apb";clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;clock-names = "pll1";clock-frequency = <2133>;};
This should go in the SoC dtsi.
- };
+};
+&gmac0_rmii_refin {
- u-boot,dm-spl;
+};
+&aoncrg {
- u-boot,dm-spl;
+};
+&syscrg {
- u-boot,dm-spl;
+};
+&stgcrg {
- u-boot,dm-spl;
+};