Re: [U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs

On Thursday, December 24, 2015 at 12:22:00 PM, Wills Wang wrote:

This patch enable work for ar933x SOC, tested on ar9331 board.

Signed-off-by: Wills Wang wills.wang@live.com

[...]

diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 3ebc202..fd50909 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -39,6 +39,7 @@ cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 +cpuflags-$(CONFIG_ARCH_ATH79) += -mtune=24kc

You can just tune it for MIPS32_R2 , it will be compatible with older toolchains too. I don't think there is much benefit in being so explicit and using mips24kc tuning.

PLATFORM_CPPFLAGS += $(cpuflags-y)

PLATFORM_CPPFLAGS += -D__MIPS__

[...]

diff --git a/arch/mips/mach-ath79/ar933x/ddr_tap.S b/arch/mips/mach-ath79/ar933x/ddr_tap.S new file mode 100644 index 0000000..18c57de --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/ddr_tap.S @@ -0,0 +1,268 @@ +/*

• • (C) Copyright 2015
• • Wills Wang, wills.wang@live.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h>

+#define DRAM_K0(x) KSEG0ADDR(x) +#define DRAM_K1(x) KSEG1ADDR(x)

• .text
• .set noreorder

+LEAF(ddr_tap_init)

• /* Tap settings for the DDR */
• li t0, 0xffffffff
• li t1, DRAM_K0(0x500000)
• sw t0, 0x0(t1)
• sw t0, 0x4(t1)
• sw t0, 0x8(t1)
• sw t0, 0xc(t1)
• nop
• nop
• li t8, DRAM_K1(0x2000)
• li t0, 0x00
• li t1, 0x100

+0:

• andi t2, t0, 0x03
• li t3, 0x00
• bne t2, t3,1f

• nop
  

• li t9, 0x00000000
• sw t9, 0x0(t8)
• b 2f

• nop
  

Please rewrite this into C, I believe it should be pretty easy.

[...]

diff --git a/arch/mips/mach-ath79/ar933x/lowlevel_init.S b/arch/mips/mach-ath79/ar933x/lowlevel_init.S new file mode 100644 index 0000000..72509ca --- /dev/null +++ b/arch/mips/mach-ath79/ar933x/lowlevel_init.S @@ -0,0 +1,460 @@ +/*

• • (C) Copyright 2015
• • Wills Wang, wills.wang@live.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <config.h> +#include <asm/asm.h> +#include <asm/regdef.h> +#include <asm/mipsregs.h> +#include <asm/addrspace.h> +#include <asm/arch/ar71xx_regs.h>

+#define SET_BIT(val, bit) ((val) | (1 << (bit))) +#define SET_PLL_PD(val) SET_BIT(val, 30) +#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16) +#define PLL_BYPASS(val) SET_BIT(val, 2)

+#define MK_PLL_CONF(divint, refdiv, range, outdiv) \

• (((0x3F & divint) << 10) | \
  

• ((0x1F & refdiv) << 16) | \
  

• ((0x1 & range)   << 21) | \
  

• ((0x7 & outdiv)  << 23) )
  

+#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \

• (((0x3 & (cpudiv - 1)) << 5) | \
• ((0x3 & (ddrdiv - 1)) << 10) | \
• ((0x3 & (ahbdiv - 1)) << 15) )

+/*

• • PLL_CPU_CONFIG_VAL
• • Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
• • After PLL configuration we need to clear this bit
• • Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
• • bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL)

• •                  =>  32  (0x20)  VCOOUT = XTAL * DIV_INT
    

• • bits 16..20 (5bit) REFDIV (Reference clock divider)

• •                  =>  1   (0x1)   [Must start at values 1]
    

• • bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL)

• •                  =>  0   (0x0)   [Doesn't impact clock values]
    

• • bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output)

• •                  =>  1   (0x1)   [0 is illegal!]
    

• •                          PLLOUT = VCOOUT * (1/2^OUTDIV)
    

• */

+/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1) +/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */ +#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1)

+/*

• • PLL_CLK_CONTROL_VAL
• • In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
• • After PLL configuration we need to clear this bit
• • Values written into CPU Clock Control Register CLOCK_CONTROL
• • bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.

• •                  Software must enable the CPU PLL for normal and
    

• •                  then set this bit to 0)
    

• • bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)

• •                  CPU_CLK = PLLOUT / CPU_POST_DIV
    

• • bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)

• •                  DDR_CLK = PLLOUT / DDR_POST_DIV
    

• • bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)

• •                  AHB_CLK = PLLOUT / AHB_POST_DIV
    

• */

+#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)

• .text
• .set noreorder

+LEAF(lowlevel_init)

• /* These three WLAN_RESET will avoid original issue */
• li t3, 0x03

+1:

• li t0, KSEG1ADDR(AR71XX_RESET_BASE)
• lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
• ori t1, t1, 0x0800
• sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
• nop
• lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
• li t2, 0xfffff7ff
• and t1, t1, t2
• sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
• nop
• addi t3, t3, -1
• bnez t3, 1b

• nop
  

This should be also easy to rewrite into C , right ?

[...]

diff --git a/arch/mips/mach-ath79/cpu.c b/arch/mips/mach-ath79/cpu.c new file mode 100644 index 0000000..1f58877 --- /dev/null +++ b/arch/mips/mach-ath79/cpu.c @@ -0,0 +1,269 @@ +/*

• • (C) Copyright 2015
• • Wills Wang, wills.wang@live.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h>

+DECLARE_GLOBAL_DATA_PTR;

+enum ath79_soc_type get_soc_type(void) +{

• enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
• u32 id, major, minor;
• id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
• major = id & REV_ID_MAJOR_MASK;
• switch (major) {
• case REV_ID_MAJOR_AR71XX:

• minor = id & AR71XX_REV_ID_MINOR_MASK;
  

• switch (minor) {
  

• case AR71XX_REV_ID_MINOR_AR7130:
  

• 	soc = ATH79_SOC_AR7130;
  

• 	break;
  

I think you can convert this stuff into a table of sorts, so you won't have such a lengthy code:

struct { u32 major; u32 minor; enum soc; } table[] { { REV_ID_MAJOR_AR71XX, AR71XX_REV_ID_MINOR_AR7130, ATH79_SOC_AR7130 }, ... }

And just iterate over such table.

[...]

+int print_cpuinfo(void) +{

• enum ath79_soc_type soc = ATH79_SOC_UNKNOWN;
• char *chip = "????";
• u32 id, major, minor;
• u32 rev = 0;
• u32 ver = 1;
• id = readl(KSEG1ADDR(AR71XX_RESET_BASE + AR71XX_RESET_REG_REV_ID));
• major = id & REV_ID_MAJOR_MASK;
• switch (major) {
• case REV_ID_MAJOR_AR71XX:

• minor = id & AR71XX_REV_ID_MINOR_MASK;
  

• rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  

• rev &= AR71XX_REV_ID_REVISION_MASK;
  

• switch (minor) {
  

• case AR71XX_REV_ID_MINOR_AR7130:
  

• 	soc = ATH79_SOC_AR7130;
  

• 	chip = "7130";
  

• 	break;
  

DTTO here, use table lookup

[...]

• return 0;

+} diff --git a/arch/mips/mach-ath79/dram.c b/arch/mips/mach-ath79/dram.c new file mode 100644 index 0000000..42539dc --- /dev/null +++ b/arch/mips/mach-ath79/dram.c @@ -0,0 +1,27 @@ +/*

• • (C) Copyright 2015
• • Wills Wang, wills.wang@live.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/addrspace.h> +#include <asm/arch/ddr.h>

+phys_size_t initdram(int board_type) +{

• uint8_t *addr, *p;
• int i;
• ddr_tap_init();
• addr = (uint8_t *)KSEG1;
• *addr = 0x77;
• for (i = 0, p = addr; p < (uint8_t *)KSEG2; i++) {

• p += 0x1000000;
  

• *p = i;
  

• if (*addr != 0x77)
  

• 	break;
  

• }

What is this and how does it work ?

• return (phys_size_t)(p - addr);

+}

[...]

diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c new file mode 100644 index 0000000..0ace05d --- /dev/null +++ b/arch/mips/mach-ath79/reset.c @@ -0,0 +1,55 @@ +/*

• • (C) Copyright 2015
• • Wills Wang, wills.wang@live.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <asm/arch/ath79.h> +#include <asm/arch/ar71xx_regs.h>

+#define REG_READ(b, o) readl(KSEG1ADDR(b + o)) +#define REG_WRITE(b, o, v) writel(v, KSEG1ADDR((b + o))) +#define RST_READ(a) REG_READ(AR71XX_RESET_BASE, a) +#define RST_WRITE(a, v) REG_WRITE(AR71XX_RESET_BASE, a, v)

Drop these.

+DECLARE_GLOBAL_DATA_PTR;

+void _machine_restart(void) +{

• enum ath79_soc_type soc;
• u32 val, reg = 0;
• soc = get_soc_type();
• if (soc_is_ar71xx(soc))

• reg = AR71XX_RESET_REG_RESET_MODULE;
  

• else if (soc_is_ar724x(soc))

• reg = AR724X_RESET_REG_RESET_MODULE;
  

• else if (soc_is_ar913x(soc))

• reg = AR913X_RESET_REG_RESET_MODULE;
  

• else if (soc_is_ar933x(soc))

• reg = AR933X_RESET_REG_RESET_MODULE;
  

• else if (soc_is_ar934x(soc))

• reg = AR934X_RESET_REG_RESET_MODULE;
  

• else if (soc_is_qca953x(soc))

• reg = QCA953X_RESET_REG_RESET_MODULE;
  

• else if (soc_is_qca955x(soc))

• reg = QCA955X_RESET_REG_RESET_MODULE;
  

• else if (soc_is_qca956x(soc))

• reg = QCA956X_RESET_REG_RESET_MODULE;
  

• else

• puts("Reset register not defined for this SOC\n");
  

• if (reg) {

• val = RST_READ(reg);
  

• val |= AR71XX_RESET_FULL_CHIP;
  

• RST_WRITE(reg, val);
  

setbits_le32() please.

• }
• while (1)

• /* NOP */;
  

+}