Re: FIT image: load secure FPGA

On 19/01/22, Adrian Fiergolski wrote:

Hi Jorge,

hi Adrian,

Have you succeeded to enable secure boot on ZynqMP with SPL (not Xilinx's FSBL)? Is it documented somewhere? Any configuration files/yocto recipes?

somewhere there: https://github.com/foundriesio/meta-lmp

Have you managed to resolve problem of the bitstream loaded in such a case by SPL?

Yes. I wrote the docs here below: https://docs.foundries.io/latest/reference-manual/security/authentication-xi...

I need to use an encrypted bitstream. However, it required the use of DeviceKeys in post-boot state which eventually requires secure boot.

Regards,

hope that helps

Adrian