[U-Boot] [PATCH] Add support for the Calao QIL-A9G20 board

The Calao SBC35-A9G20 board is manufactured and sold by Calao Systems http://www.calao-systems.com. It is built around an AT91SAM9G20 ARM SoC running at 400MHz. It features an Ethernet port, an SPI RTC backed by an onboard battery , an SD/MMC slot, a CompactFlash slot, 64Mo of SDRAM, 256Mo of NAND flash, two USB host ports, and an USB device port. More informations can be found at http://www.calao-systems.com/articles.php?lng=en&pg=5936

Signed-off-by: Albin Tonnerre albin.tonnerre@free-electrons.com --- MAINTAINERS | 2 + MAKEALL | 2 + Makefile | 10 ++ board/calao/qil_a9g20/Makefile | 55 ++++++++++ board/calao/qil_a9g20/config.mk | 1 + board/calao/qil_a9g20/qil_a9g20.c | 201 +++++++++++++++++++++++++++++++++++++ board/calao/qil_a9g20/spi.c | 57 +++++++++++ include/configs/qil_a9g20.h | 200 ++++++++++++++++++++++++++++++++++++ 8 files changed, 528 insertions(+), 0 deletions(-) create mode 100644 board/calao/qil_a9g20/Makefile create mode 100644 board/calao/qil_a9g20/config.mk create mode 100644 board/calao/qil_a9g20/qil_a9g20.c create mode 100644 board/calao/qil_a9g20/spi.c create mode 100644 include/configs/qil_a9g20.h

diff --git a/MAINTAINERS b/MAINTAINERS index e9db278..b1e82f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -696,6 +696,8 @@ Andrea Scian andrea.scian@dave-tech.it

Albin Tonnerre albin.tonnerre@free-electrons.com

+ qil_a9260 ARM926EJS (AT91SAM9260 SoC) + qil_a9g20 ARM926EJS (AT91SAM9G20 SoC) sbc35_a9g20 ARM926EJS (AT91SAM9G20 SoC) tny_a9260 ARM926EJS (AT91SAM9260 SoC) tny_a9g20 ARM926EJS (AT91SAM9G20 SoC) diff --git a/MAKEALL b/MAKEALL index f0ed8ea..531a667 100755 --- a/MAKEALL +++ b/MAKEALL @@ -614,6 +614,8 @@ LIST_at91=" \ m501sk \ pm9261 \ pm9263 \ + QIL_A9260 \ + QIL_A9G20 \ SBC35_A9G20 \ TNY_A9260 \ TNY_A9G20 \ diff --git a/Makefile b/Makefile index 0449a5b..eb542a4 100644 --- a/Makefile +++ b/Makefile @@ -2897,6 +2897,16 @@ at91sam9g45ekes_config : unconfig pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91

+QIL_A9G20_NANDFLASH_config \ +QIL_A9G20_EEPROM_config \ +QIL_A9G20_config \ +QIL_A9260_NANDFLASH_config \ +QIL_A9260_EEPROM_config \ +QIL_A9260_config : unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h + @$(MKCONFIG) -a qil_a9g20 arm arm926ejs qil_a9g20 calao at91 + SBC35_A9G20_NANDFLASH_config \ SBC35_A9G20_EEPROM_config \ SBC35_A9G20_config : unconfig diff --git a/board/calao/qil_a9g20/Makefile b/board/calao/qil_a9g20/Makefile new file mode 100644 index 0000000..07783bf --- /dev/null +++ b/board/calao/qil_a9g20/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop stelian.pop@leadtechdesign.com +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += qil_a9g20.o +COBJS-$(CONFIG_ATMEL_SPI) += spi.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/calao/qil_a9g20/config.mk b/board/calao/qil_a9g20/config.mk new file mode 100644 index 0000000..ff2cfd1 --- /dev/null +++ b/board/calao/qil_a9g20/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/calao/qil_a9g20/qil_a9g20.c b/board/calao/qil_a9g20/qil_a9g20.c new file mode 100644 index 0000000..38f4cce --- /dev/null +++ b/board/calao/qil_a9g20/qil_a9g20.c @@ -0,0 +1,201 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop stelian.pop@leadtechdesign.com + * Lead Tech Design <www.leadtechdesign.com> + * + * Copyright (C) 2009 + * Albin Tonnerre, Free-Electrons albin.tonnerre@free-electrons.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void qil_a9g20_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void qil_a9g20_macb_hw_init(void) +{ + unsigned long rstc; + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + + /* + * Disable pull-up on: + * RXDV (PA17) => PHY normal mode (not Test mode) + * ERX0 (PA14) => PHY ADDR0 + * ERX1 (PA15) => PHY ADDR1 + * ERX2 (PA25) => PHY ADDR2 + * ERX3 (PA26) => PHY ADDR3 + * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + + rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + + /* Need to reset PHY -> 500ms reset */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0D << 8)) | + AT91_RSTC_URSTEN); + + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + + /* Wait for end hardware reset */ + while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (rstc) | + AT91_RSTC_URSTEN); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA14) | + pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA17) | + pin_to_mask(AT91_PIN_PA25) | + pin_to_mask(AT91_PIN_PA26) | + pin_to_mask(AT91_PIN_PA28), + pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + + at91_macb_hw_init(); +} +#endif + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + +#ifdef CONFIG_QIL_A9G20 + gd->bd->bi_arch_number = MACH_TYPE_QIL_A9G20; +#else + gd->bd->bi_arch_number = MACH_TYPE_QIL_A9260; +#endif + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); + qil_a9g20_nand_hw_init(); +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 4 | 1 << 5); +#endif +#ifdef CONFIG_MACB + qil_a9g20_macb_hw_init(); +#endif + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) + return -1; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); +#endif + return rc; +} diff --git a/board/calao/qil_a9g20/spi.c b/board/calao/qil_a9g20/spi.c new file mode 100644 index 0000000..035a89f --- /dev/null +++ b/board/calao/qil_a9g20/spi.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2009 + * Albin Tonnerre, Free Electrons albin.tonnerre@free-electrons.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <spi.h> + +#define QIL_A9G20_CS0_PIN AT91_PIN_PA3 +#define QIL_A9G20_CS1_PIN AT91_PIN_PC11 + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && (cs == 1 || cs == 0); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + if(slave->cs == 0) + at91_set_gpio_value(QIL_A9G20_CS0_PIN, 0); + else if(slave->cs == 1) + at91_set_gpio_value(QIL_A9G20_CS1_PIN, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + if(slave->cs == 0) + at91_set_gpio_value(QIL_A9G20_CS0_PIN, 1); + else if(slave->cs == 1) + at91_set_gpio_value(QIL_A9G20_CS1_PIN, 1); +} + +void spi_init_f(void) +{ + /* everything done in board_init */ +} diff --git a/include/configs/qil_a9g20.h b/include/configs/qil_a9g20.h new file mode 100644 index 0000000..f6568a5 --- /dev/null +++ b/include/configs/qil_a9g20.h @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2009 + * Albin Tonnerre, Free Electrons albin.tonnerre@free-electrons.com + * + * Configuation settings for the Calao QIL-A9G20 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if defined(CONFIG_QIL_A9G20_NANDFLASH) || defined(CONFIG_QIL_A9G20_EEPROM) +#define CONFIG_QIL_A9G20 +#elif defined(CONFIG_QIL_A9260_NANDFLASH) || defined(CONFIG_QIL_A9260_EEPROM) +#define CONFIG_QIL_A9260 +#endif + +#ifdef CONFIG_QIL_A9G20 +#define CONFIG_AT91SAM9G20 +#else +#define CONFIG_AT91SAM9260 +#endif + +#if defined(CONFIG_QIL_A9G20_NANDFLASH) || defined(CONFIG_QIL_A9260_NANDFLASH) +#define CONFIG_ENV_IS_IN_NAND +#else +#define CONFIG_ENV_IS_IN_EEPROM +#endif + +/* ARM asynchronous clock */ +#define AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */ +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#undef CONFIG_USART3 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* SPI EEPROM */ +#define CONFIG_SPI +#define CONFIG_CMD_SPI +#define CONFIG_ATMEL_SPI +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) + +#define CONFIG_CMD_EEPROM +#define CONFIG_SPI_M95XXX +#define CONFIG_SYS_EEPROM_SIZE 0x10000 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 + +/* SPI RTC */ +#define CONFIG_CMD_DATE +#define CONFIG_RTC_M41T94 +#define CONFIG_M41T94_SPI_BUS 0 +#define CONFIG_M41T94_SPI_CS 0 + +/* NAND flash */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 + +/* NOR flash - no real flash on this board */ +#define CONFIG_SYS_NO_FLASH 1 + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MACB_SEARCH_PHY 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_CMD_FAT 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +/* Env in EEPROM, bootstrap + u-boot in NAND*/ +#ifdef CONFIG_ENV_IS_IN_EEPROM +#define CONFIG_ENV_OFFSET 0x20 +#define CONFIG_ENV_SIZE 0x1000 +#endif + +/* Env, bootstrap and u-boot in NAND */ +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 +#endif + +#define CONFIG_BOOTCOMMAND "nboot 0x21000000 0 400000" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock1 " \ + "mtdparts=atmel_nand:16M(kernel)ro," \ + "120M(rootfs),-(other) " \ + "rw rootfstype=jffs2" + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif