Re: [PATCH v3 5/7] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY

On Thu, 27 Apr 2023 at 13:05, Eugen Hristev eugen.hristev@collabora.com wrote:

From: Joseph Chen chenjh@rock-chips.com

Add the node for PCIe 2x1l 2 device together with the corresponding combphy.

Signed-off-by: Joseph Chen chenjh@rock-chips.com [eugen.hristev@collabora.com: moved to -u-boot.dtsi, minor adaptations] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com [jonas@kwiboo.se: adapt to kernel node] Signed-off-by: Jonas Karlman jonas@kwiboo.se

---

Changes in v3:

• s/pciE/PCIe/

Changes in v2:

• add compliance with linux by Jonas

arch/arm/dts/rk3588s-u-boot.dtsi | 77 ++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+)

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index ad652c02e58e..6385da1471a5 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -4,6 +4,7 @@ */

#include "rockchip-u-boot.dtsi" +#include <dt-bindings/phy/phy.h>

/ { dmc { @@ -58,6 +59,11 @@ reg = <0x0 0xfd58a000 0x0 0x2000>; };

•   pipe_phy0_grf: syscon@fd5bc000 {
  

•           compatible = "rockchip,pipe-phy-grf", "syscon";
  

•           reg = <0x0 0xfd5bc000 0x0 0x100>;
  

•   };
  

•   usb2phy2_grf: syscon@fd5d8000 {
            compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
                         "simple-mfd";
  

@@ -104,6 +110,61 @@ }; };

•   pcie2x1l2: pcie@fe190000 {
  

•           compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
  

•           #address-cells = <3>;
  

•           #size-cells = <2>;
  

•           bus-range = <0x40 0x4f>;
  

•           clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
  

•                    <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
  

•                    <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
  

•           clock-names = "aclk_mst", "aclk_slv",
  

•                         "aclk_dbi", "pclk",
  

•                         "aux", "pipe";
  

•           device_type = "pci";
  

•           interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
  

•                        <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
  

•                        <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
  

•                        <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
  

•                        <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
  

•           interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  

•           #interrupt-cells = <1>;
  

•           interrupt-map-mask = <0 0 0 7>;
  

•           interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
  

•                           <0 0 0 2 &pcie2x1l2_intc 1>,
  

•                           <0 0 0 3 &pcie2x1l2_intc 2>,
  

•                           <0 0 0 4 &pcie2x1l2_intc 3>;
  

•           linux,pci-domain = <4>;
  

•           num-ib-windows = <8>;
  

•           num-ob-windows = <8>;
  

•           num-viewport = <4>;
  

•           max-link-speed = <2>;
  

•           msi-map = <0x4000 &gic 0x4000 0x1000>;
  

•           num-lanes = <1>;
  

•           phys = <&combphy0_ps PHY_TYPE_PCIE>;
  

•           phy-names = "pcie-phy";
  

•           power-domains = <&power RK3588_PD_PCIE>;
  

•           ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
  

•                    <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
  

•                    <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
  

•           reg = <0xa 0x41000000 0x0 0x00400000>,
  

•                 <0x0 0xfe190000 0x0 0x00010000>,
  

•                 <0x0 0xf4000000 0x0 0x00100000>;
  

•           reg-names = "dbi", "apb", "config";
  

•           resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
  

•           reset-names = "pcie", "periph";
  

•           rockchip,pipe-grf = <&php_grf>;
  

•           status = "disabled";
  

•           pcie2x1l2_intc: legacy-interrupt-controller {
  

•                   interrupt-controller;
  

•                   #address-cells = <0>;
  

•                   #interrupt-cells = <1>;
  

•                   interrupt-parent = <&gic>;
  

•                   interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
  

•           };
  

•   };
  

Look like we are growing non-linux dt in -u-boot.dtsi. This might not be a good choice in the long run. I understand the importance of this SoC but code maintenance must be in a generic way.

Thanks, Jagan.