The HRCW (hardware reset configuration word) is a constant that must be hard-coded into the boot loader image. So, it must be available at compile time, and cannot be migrated to the DT mechanism, but has to be kept in Kconfig.
Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these.
Signed-off-by: Mario Six mario.six@gdsys.cc --- arch/powerpc/cpu/mpc83xx/Kconfig | 69 +++ arch/powerpc/cpu/mpc83xx/hrcw/Kconfig | 816 ++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h | 37 ++ arch/powerpc/cpu/mpc83xx/start.S | 2 + board/freescale/mpc8315erdb/MAINTAINERS | 1 + board/freescale/mpc8349emds/MAINTAINERS | 1 + board/freescale/mpc8349itx/mpc8349itx.c | 2 + board/freescale/mpc837xemds/MAINTAINERS | 1 + configs/MPC8308RDB_defconfig | 7 + configs/MPC8313ERDB_33_defconfig | 8 + configs/MPC8313ERDB_66_defconfig | 7 + configs/MPC8313ERDB_NAND_33_defconfig | 7 + configs/MPC8313ERDB_NAND_66_defconfig | 6 + configs/MPC8315ERDB_defconfig | 8 + configs/MPC8323ERDB_defconfig | 6 + configs/MPC832XEMDS_ATM_defconfig | 6 + configs/MPC832XEMDS_HOST_33_defconfig | 6 + configs/MPC832XEMDS_HOST_66_defconfig | 6 + configs/MPC832XEMDS_SLAVE_defconfig | 3 + configs/MPC832XEMDS_defconfig | 6 + configs/MPC8349EMDS_PCI64_defconfig | 32 ++ configs/MPC8349EMDS_SDRAM_defconfig | 10 + configs/MPC8349EMDS_SLAVE_defconfig | 12 +- configs/MPC8349EMDS_defconfig | 10 + configs/MPC8349ITXGP_defconfig | 10 + configs/MPC8349ITX_LOWBOOT_defconfig | 10 + configs/MPC8349ITX_defconfig | 9 + configs/MPC837XEMDS_HOST_defconfig | 10 + configs/MPC837XEMDS_SLAVE_defconfig | 33 ++ configs/MPC837XEMDS_defconfig | 10 + configs/MPC837XERDB_SLAVE_defconfig | 7 + configs/MPC837XERDB_defconfig | 10 + configs/TQM834x_defconfig | 9 + configs/caddy2_defconfig | 10 + configs/hrcon_defconfig | 6 + configs/hrcon_dh_defconfig | 6 + configs/ids8313_defconfig | 3 + configs/kmcoge5ne_defconfig | 9 + configs/kmeter1_defconfig | 9 + configs/kmopti2_defconfig | 4 + configs/kmsupx5_defconfig | 4 + configs/kmtegr1_defconfig | 5 + configs/kmtepr2_defconfig | 4 + configs/kmvect1_defconfig | 5 + configs/mpc8308_p1m_defconfig | 5 + configs/sbc8349_PCI_33_defconfig | 10 + configs/sbc8349_PCI_66_defconfig | 10 + configs/sbc8349_defconfig | 10 + configs/strider_con_defconfig | 5 + configs/strider_con_dp_defconfig | 5 + configs/strider_cpu_defconfig | 5 + configs/strider_cpu_dp_defconfig | 5 + configs/suvd3_defconfig | 4 + configs/tuge1_defconfig | 4 + configs/tuxx1_defconfig | 4 + configs/ve8313_defconfig | 7 + configs/vme8349_defconfig | 10 + include/configs/MPC8308RDB.h | 32 -- include/configs/MPC8313ERDB_NAND.h | 38 -- include/configs/MPC8313ERDB_NOR.h | 40 -- include/configs/MPC8315ERDB.h | 34 -- include/configs/MPC8323ERDB.h | 24 - include/configs/MPC832XEMDS.h | 37 -- include/configs/MPC8349EMDS.h | 86 ---- include/configs/MPC8349EMDS_SDRAM.h | 86 ---- include/configs/MPC8349ITX.h | 39 -- include/configs/MPC837XEMDS.h | 42 -- include/configs/MPC837XERDB.h | 40 -- include/configs/TQM834x.h | 35 -- include/configs/caddy2.h | 41 -- include/configs/hrcon.h | 32 -- include/configs/ids8313.h | 21 - include/configs/kmcoge5ne.h | 19 - include/configs/kmeter1.h | 19 - include/configs/kmopti2.h | 22 - include/configs/kmsupx5.h | 22 - include/configs/kmtegr1.h | 22 - include/configs/kmtepr2.h | 22 - include/configs/kmvect1.h | 22 - include/configs/mpc8308_p1m.h | 32 -- include/configs/sbc8349.h | 71 --- include/configs/strider.h | 32 -- include/configs/suvd3.h | 22 - include/configs/tuge1.h | 22 - include/configs/tuxx1.h | 22 - include/configs/ve8313.h | 19 - include/configs/vme8349.h | 43 -- 87 files changed, 1325 insertions(+), 1039 deletions(-) create mode 100644 arch/powerpc/cpu/mpc83xx/hrcw/Kconfig create mode 100644 arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h create mode 100644 configs/MPC8349EMDS_PCI64_defconfig create mode 100644 configs/MPC837XEMDS_SLAVE_defconfig
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index bd4e5c14a9..1206c687cc 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -177,30 +177,79 @@ config TARGET_STRIDER
endchoice
+config MPC83XX_QUICC_ENGINE + bool + +# TODO: Imply MPC83xx PCI driver +config MPC83XX_PCI_SUPPORT + bool + +# TODO: Imply TSEC driver +config MPC83XX_TSEC1_SUPPORT + bool + +config MPC83XX_TSEC2_SUPPORT + bool + +config MPC83XX_PCIE1_SUPPORT + bool + +config MPC83XX_PCIE2_SUPPORT + bool + +config MPC83XX_SDHC_SUPPORT + bool + +config MPC83XX_SATA_SUPPORT + bool + +config MPC83XX_SECOND_I2C_SUPPORT + bool + +config MPC83XX_LDP_PIN + bool + config ARCH_MPC830X bool + select MPC83XX_SDHC_SUPPORT
config ARCH_MPC8308 bool select ARCH_MPC830X + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC8309 bool select ARCH_MPC830X + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC831X bool + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT
config ARCH_MPC8313 bool select ARCH_MPC831X + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC8315 bool select ARCH_MPC831X + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_PCIE2_SUPPORT + select MPC83XX_SATA_SUPPORT
config ARCH_MPC832X bool + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT
config ARCH_MPC834X bool @@ -208,12 +257,32 @@ config ARCH_MPC834X config ARCH_MPC8349 bool select ARCH_MPC834X + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC8360 bool + select MPC83XX_QUICC_ENGINE + select MPC83XX_PCI_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT
config ARCH_MPC837X bool + select MPC83XX_PCI_SUPPORT + select MPC83XX_TSEC1_SUPPORT + select MPC83XX_TSEC2_SUPPORT + select MPC83XX_PCIE1_SUPPORT + select MPC83XX_PCIE2_SUPPORT + select MPC83XX_SDHC_SUPPORT + select MPC83XX_SATA_SUPPORT + select MPC83XX_LDP_PIN + select MPC83XX_SECOND_I2C_SUPPORT + +source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
menu "Legacy options"
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig new file mode 100644 index 0000000000..c657a47b11 --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig @@ -0,0 +1,816 @@ +menu "Reset Configuration Word" + +choice + prompt "Local bus memory controller clock mode" + +config LBMC_CLOCK_MODE_1_1 + bool "1 : 1" + +config LBMC_CLOCK_MODE_1_2 + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 2" + +endchoice + +choice + prompt "DDR SDRAM memory controller clock mode" + +config DDR_MC_CLOCK_MODE_1_2 + bool "1 : 2" + +config DDR_MC_CLOCK_MODE_1_1 + depends on ARCH_MPC8315 || ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "1 : 1" + +endchoice + +if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 + +choice + prompt "System PLL VCO division" + +config SYSTEM_PLL_VCO_DIV_1 + depends on !ARCH_MPC837X + bool "1" + +config SYSTEM_PLL_VCO_DIV_2 + bool "2" + +config SYSTEM_PLL_VCO_DIV_4 + depends on !ARCH_MPC831X + bool "4" + +config SYSTEM_PLL_VCO_DIV_8 + depends on !ARCH_MPC831X + bool "8" + +endchoice + +endif + +choice + prompt "System PLL multiplication factor" + +config SYSTEM_PLL_FACTOR_2_1 + bool "2 : 1" + +config SYSTEM_PLL_FACTOR_3_1 + bool "3 : 1" + +config SYSTEM_PLL_FACTOR_4_1 + bool "4 : 1" + +config SYSTEM_PLL_FACTOR_5_1 + bool "5 : 1" + +config SYSTEM_PLL_FACTOR_6_1 + bool "6 : 1" + +config SYSTEM_PLL_FACTOR_7_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "7 : 1" + +config SYSTEM_PLL_FACTOR_8_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "8 : 1" + +config SYSTEM_PLL_FACTOR_9_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "9 : 1" + +config SYSTEM_PLL_FACTOR_10_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "10 : 1" + +config SYSTEM_PLL_FACTOR_11_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "11 : 1" + +config SYSTEM_PLL_FACTOR_12_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "12 : 1" + +config SYSTEM_PLL_FACTOR_13_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "13 : 1" + +config SYSTEM_PLL_FACTOR_14_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "14 : 1" + +config SYSTEM_PLL_FACTOR_15_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X + bool "15 : 1" + +config SYSTEM_PLL_FACTOR_16_1 + depends on ARCH_MPC8349 || ARCH_MPV8360 + bool "16 : 1" + +endchoice + +config CORE_PLL_BYPASS + bool "Core PLL bypassed" + +if !CORE_PLL_BYPASS + +choice + prompt "Core PLL Ratio" + +config CORE_PLL_RATIO_1_1 + bool "1 : 1" + +config CORE_PLL_RATIO_15_1 + bool "1.5 : 1" + +config CORE_PLL_RATIO_2_1 + bool "2 : 1" + +config CORE_PLL_RATIO_25_1 + bool "2.5 : 1" + +config CORE_PLL_RATIO_3_1 + bool "3 : 1" + +endchoice + +choice + prompt "Core PLL VCO Divider" + +config CORE_PLL_VCO_DIVIDER_2 + bool "2" + +config CORE_PLL_VCO_DIVIDER_4 + bool "4" + +config CORE_PLL_VCO_DIVIDER_8 + depends on !ARCH_MPC8315 + bool "8" + +endchoice + +endif + +if MPC83XX_QUICC_ENGINE + +choice + prompt "QUICC Engine PLL VCO Divider" + +config QUICC_VCO_DIVIDER_2 + bool "2" + +config QUICC_VCO_DIVIDER_4 + bool "4" + +config QUICC_VCO_DIVIDER_8 + depends on ARCH_MPC8309 + bool "8" + +endchoice + +choice + prompt "QUICC Engine PLL division factor" + +config QUICC_DIV_FACTOR_1 + bool "1" + +config QUICC_DIV_FACTOR_2 + bool "2" + +endchoice + +choice + prompt "QUICC Engine PLL multiplication factor" + +config QUICC_MULT_FACTOR_2 + bool "2" + +config QUICC_MULT_FACTOR_3 + bool "3" + +config QUICC_MULT_FACTOR_4 + bool "4" + +config QUICC_MULT_FACTOR_5 + bool "5" + +config QUICC_MULT_FACTOR_6 + bool "6" + +config QUICC_MULT_FACTOR_7 + bool "7" + +config QUICC_MULT_FACTOR_8 + bool "8" + +config QUICC_MULT_FACTOR_9 + depends on ARCH_MPC8360 + bool "9" + +config QUICC_MULT_FACTOR_10 + depends on ARCH_MPC8360 + bool "10" + +config QUICC_MULT_FACTOR_11 + depends on ARCH_MPC8360 + bool "11" + +config QUICC_MULT_FACTOR_12 + depends on ARCH_MPC8360 + bool "12" + +config QUICC_MULT_FACTOR_13 + depends on ARCH_MPC8360 + bool "13" + +config QUICC_MULT_FACTOR_14 + depends on ARCH_MPC8360 + bool "14" + +config QUICC_MULT_FACTOR_15 + depends on ARCH_MPC8360 + bool "15" + +config QUICC_MULT_FACTOR_16 + depends on ARCH_MPC8360 + bool "16" + +config QUICC_MULT_FACTOR_17 + depends on ARCH_MPC8360 + bool "17" + +config QUICC_MULT_FACTOR_18 + depends on ARCH_MPC8360 + bool "18" + +config QUICC_MULT_FACTOR_19 + depends on ARCH_MPC8360 + bool "19" + +config QUICC_MULT_FACTOR_20 + depends on ARCH_MPC8360 + bool "20" + +config QUICC_MULT_FACTOR_21 + depends on ARCH_MPC8360 + bool "21" + +config QUICC_MULT_FACTOR_22 + depends on ARCH_MPC8360 + bool "22" + +config QUICC_MULT_FACTOR_23 + depends on ARCH_MPC8360 + bool "23" + +config QUICC_MULT_FACTOR_24 + depends on ARCH_MPC8360 + bool "24" + +config QUICC_MULT_FACTOR_25 + depends on ARCH_MPC8360 + bool "25" + +config QUICC_MULT_FACTOR_26 + depends on ARCH_MPC8360 + bool "26" + +config QUICC_MULT_FACTOR_27 + depends on ARCH_MPC8360 + bool "27" + +config QUICC_MULT_FACTOR_28 + depends on ARCH_MPC8360 + bool "28" + +config QUICC_MULT_FACTOR_29 + depends on ARCH_MPC8360 + bool "29" + +config QUICC_MULT_FACTOR_30 + depends on ARCH_MPC8360 + bool "30" + +config QUICC_MULT_FACTOR_31 + depends on ARCH_MPC8360 + bool "31" + +endchoice + +endif + +if MPC83XX_PCI_SUPPORT + +choice + prompt "PCI host mode" + +config PCI_HOST_MODE_DISABLE + bool "Disabled" + +config PCI_HOST_MODE_ENABLE + bool "Enabled" + +endchoice + +if ARCH_MPC8349 + +choice + prompt "PCI 64-bit mode" + +config PCI_64BIT_MODE_DISABLE + bool "Disabled" + +config PCI_64BIT_MODE_ENABLE + bool "Enabled" + +endchoice + +endif + +choice + prompt "PCI internal arbiter 1 mode" + +config PCI_INT_ARBITER1_DISABLE + bool "Disabled" + +config PCI_INT_ARBITER1_ENABLE + bool "Enabled" + +endchoice + +if ARCH_MPC8349 + +choice + prompt "PCI internal arbiter 2 mode" + +config PCI_INT_ARBITER2_DISABLE + bool "Disabled" + +config PCI_INT_ARBITER2_ENABLE + bool "Enabled" + +endchoice + +endif + +if ARCH_MPC8360 + +choice + prompt "PCI clock output drive" + +config PCI_CLOCK_OUTPUT_DRIVE_DISABLE + bool "Disabled" + +config PCI_CLOCK_OUTPUT_DRIVE_ENABLE + bool "Enabled" + +endchoice + +endif + +endif + +choice + prompt "Core disable mode" + +config CORE_DISABLE_MODE_OFF + bool "Off" + +config CORE_DISABLE_MODE_ON + bool "On" + +endchoice + +choice + prompt "Boot Memory Space" + +config BOOT_MEMORY_SPACE_HIGH + bool "High" + +config BOOT_MEMORY_SPACE_LOW + bool "Low" + +endchoice + +choice + prompt "Boot Sequencer Configuration" + +config BOOT_SEQUENCER_DISABLED + bool "Disabled" + +config BOOT_SEQUENCER_NORMAL_I2C + bool "Normal I2C" + +config BOOT_SEQUENCER_EXTENDED_I2C + bool "Extended I2C" + +endchoice + +choice + prompt "Software Watchdog" + +config SOFTWARE_WATCHDOG_DISABLED + bool "Disabled" + +config SOFTWARE_WATCHDOG_ENABLED + bool "Enabled" + +endchoice + +choice + prompt "Boot ROM interface location" + +config BOOT_ROM_INTERFACE_DDR_SDRAM + bool "DDR_SDRAM" + +config BOOT_ROM_INTERFACE_PCI1 + depends on MPC83XX_PCI_SUPPORT + bool "PCI1" + +config BOOT_ROM_INTERFACE_PCI2 + depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349 + bool "PCI2" + +config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM + depends on ARCH_MPC837X + bool "PCI2" + +config BOOT_ROM_INTERFACE_ESDHC + depends on ARCH_MPC8309 + bool "eSDHC" + +config BOOT_ROM_INTERFACE_SPI + depends on ARCH_MPC8309 + bool "SPI" + +config BOOT_ROM_INTERFACE_GPCM_8BIT + bool "Local bus GPCM - 8-bit ROM" + +config BOOT_ROM_INTERFACE_GPCM_16BIT + bool "Local bus GPCM - 16-bit ROM" + +config BOOT_ROM_INTERFACE_GPCM_32BIT + depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X + bool "Local bus GPCM - 32-bit ROM" + +config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit small page ROM" + +config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE + depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 + bool "Local bus NAND Flash- 8-bit large page ROM" + +endchoice + +if MPC83XX_TSEC1_SUPPORT + +choice + prompt "TSEC1 mode" + +config TSEC1_MODE_MII + depends on !ARCH_MPC8349 + bool "MII" + +config TSEC1_MODE_RMII + depends on ARCH_MPC831X && !ARCH_MPC8349 + bool "RMII" + +config TSEC1_MODE_RGMII + bool "RGMII" + +config TSEC1_MODE_RTBI + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +config TSEC1_MODE_GMII + depends on ARCH_MPC8349 + bool "GMII" + +config TSEC1_MODE_TBI + depends on ARCH_MPC8349 + bool "TBI" + +config TSEC1_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" + +endchoice + +endif + +if MPC83XX_TSEC2_SUPPORT + +choice + prompt "TSEC2 mode" + +config TSEC2_MODE_MII + depends on !ARCH_MPC8349 + bool "MII" + +config TSEC2_MODE_RMII + depends on ARCH_MPC831X && !ARCH_MPC8349 + bool "RMII" + +config TSEC2_MODE_RGMII + bool "RGMII" + +config TSEC2_MODE_RTBI + depends on ARCH_MPC831X || ARCH_MPC837X + bool "RTBI" + +config TSEC2_MODE_GMII + depends on ARCH_MPC8349 + bool "GMII" + +config TSEC2_MODE_TBI + depends on ARCH_MPC8349 + bool "TBI" + +config TSEC2_MODE_SGMII + depends on ARCH_MPC831X || ARCH_MPC837X + bool "SGMII" + +endchoice + +endif + +choice + prompt "True litle-endian mode" + +config TRUE_LITTLE_ENDIAN_BIG_ENDIAN + bool "Big-endian" + +config TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN + bool "Little-endian" + +endchoice + +if ARCH_MPC8360 + +choice + prompt "Secondary DDR IO" + +config SECONDARY_DDR_IO_DISABLE + bool "Disable" + +config SECONDARY_DDR_IO_ENABLE + bool "Enable" + +endchoice + +endif + +if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 + +choice + prompt "LALE timing" + +config LALE_TIMING_NORMAL + bool "Normal" + +config LALE_TIMING_EARLIER + bool "Earlier" + +endchoice + +endif + +if MPC83XX_LDP_PIN + +choice + prompt "LDP pin mux state" + +config LDP_PIN_MUX_STATE_1 + bool "Inital value 1" + +config LDP_PIN_MUX_STATE_0 + bool "Inital value 0" + +endchoice + +endif + +endmenu + +config LBMC_CLOCK_MODE + int + default 0 if LBMC_CLOCK_MODE_1_1 + default 1 if LBMC_CLOCK_MODE_1_2 + +config DDR_MC_CLOCK_MODE + int + default 1 if DDR_MC_CLOCK_MODE_1_2 + default 0 if DDR_MC_CLOCK_MODE_1_1 + +config SYSTEM_PLL_VCO_DIV + int + default 0 if ARCH_MPC8349 || ARCH_MPC832X + default 2 if ARCH_MPC8313 + default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X + default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X + default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X + default 0 if SYSTEM_PLL_VCO_DIV_4 && (ARCH_MPC8360 || ARCH_MPC837X) + default 1 if SYSTEM_PLL_VCO_DIV_8 && (ARCH_MPC8360 || ARCH_MPC837X) + default 2 if SYSTEM_PLL_VCO_DIV_2 && (ARCH_MPC8360 || ARCH_MPC837X) + default 3 if SYSTEM_PLL_VCO_DIV_1 + +config SYSTEM_PLL_FACTOR + int + default 2 if SYSTEM_PLL_FACTOR_2_1 + default 3 if SYSTEM_PLL_FACTOR_3_1 + default 4 if SYSTEM_PLL_FACTOR_4_1 + default 5 if SYSTEM_PLL_FACTOR_5_1 + default 6 if SYSTEM_PLL_FACTOR_6_1 + default 7 if SYSTEM_PLL_FACTOR_7_1 + default 8 if SYSTEM_PLL_FACTOR_8_1 + default 9 if SYSTEM_PLL_FACTOR_9_1 + default 10 if SYSTEM_PLL_FACTOR_10_1 + default 11 if SYSTEM_PLL_FACTOR_11_1 + default 12 if SYSTEM_PLL_FACTOR_12_1 + default 13 if SYSTEM_PLL_FACTOR_13_1 + default 14 if SYSTEM_PLL_FACTOR_14_1 + default 15 if SYSTEM_PLL_FACTOR_15_1 + default 0 if SYSTEM_PLL_FACTOR_16_1 + +config CORE_PLL_RATIO + hex + default 0x0 if CORE_PLL_BYPASS + default 0x02 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x22 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x42 if CORE_PLL_RATIO_1_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x03 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x23 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x43 if CORE_PLL_RATIO_15_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x04 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x24 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x44 if CORE_PLL_RATIO_2_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x05 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x25 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x45 if CORE_PLL_RATIO_25_1 && CORE_PLL_VCO_DIVIDER_8 + default 0x06 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_2 + default 0x26 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_4 + default 0x46 if CORE_PLL_RATIO_3_1 && CORE_PLL_VCO_DIVIDER_8 + +config CORE_DISABLE_MODE + int + default 0 if CORE_DISABLE_MODE_OFF + default 1 if CORE_DISABLE_MODE_ON + +config BOOT_MEMORY_SPACE + int + default 0 if BOOT_MEMORY_SPACE_LOW + default 1 if BOOT_MEMORY_SPACE_HIGH + +config BOOT_SEQUENCER + int + default 0 if BOOT_SEQUENCER_DISABLED + default 1 if BOOT_SEQUENCER_NORMAL_I2C + default 2 if BOOT_SEQUENCER_EXTENDED_I2C + +config SOFTWARE_WATCHDOG + int + default 0 if SOFTWARE_WATCHDOG_DISABLED + default 1 if SOFTWARE_WATCHDOG_ENABLED + +config BOOT_ROM_INTERFACE + hex + default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM + default 0x4 if BOOT_ROM_INTERFACE_PCI1 + default 0x8 if BOOT_ROM_INTERFACE_PCI2 + default 0x8 if BOOT_ROM_INTERFACE_ESDHC + default 0xc if BOOT_ROM_INTERFACE_SPI + default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM + default 0x14 if BOOT_ROM_INTERFACE_GPCM_8BIT + default 0x18 if BOOT_ROM_INTERFACE_GPCM_16BIT + default 0x1c if BOOT_ROM_INTERFACE_GPCM_32BIT + default 0x5 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL + default 0x15 if BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE + +config TSEC1_MODE + hex + default 0x0 if !MPC83XX_TSEC1_SUPPORT + default 0x0 if TSEC1_MODE_MII + default 0x1 if TSEC1_MODE_RMII + default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 + default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 + default 0x6 if TSEC1_MODE_SGMII + default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349 + default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349 + default 0x2 if TSEC1_MODE_GMII + default 0x3 if TSEC1_MODE_TBI + +config TSEC2_MODE + hex + default 0x0 if !MPC83XX_TSEC2_SUPPORT + default 0x0 if TSEC2_MODE_MII + default 0x1 if TSEC2_MODE_RMII + default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 + default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 + default 0x6 if TSEC2_MODE_SGMII + default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349 + default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349 + default 0x2 if TSEC2_MODE_GMII + default 0x3 if TSEC2_MODE_TBI + +config SECONDARY_DDR_IO + int + default 0 if !ARCH_MPC8360 + default 0 if SECONDARY_DDR_IO_DISABLE + default 1 if SECONDARY_DDR_IO_ENABLE + +config TRUE_LITTLE_ENDIAN + int + default 0 if TRUE_LITTLE_ENDIAN_BIG_ENDIAN + default 1 if TRUE_LITTLE_ENDIAN_LITTLE_ENDIAN + +config LALE_TIMING + int + default 0 if ARCH_MPC830X || ARCH_MPC837X + default 0 if LALE_TIMING_NORMAL + default 1 if LALE_TIMING_EARLIER + +config LDP_PIN_MUX_STATE + int + default 0 if !MPC83XX_LDP_PIN + default 0 if LDP_PIN_MUX_STATE_1 + default 1 if LDP_PIN_MUX_STATE_0 + +config QUICC_VCO_DIVIDER + int + default 0 if !MPC83XX_QUICC_ENGINE + default 0 if QUICC_VCO_DIVIDER_2 && ARCH_MPC8309 + default 1 if QUICC_VCO_DIVIDER_4 && ARCH_MPC8309 + default 2 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8309 + default 2 if QUICC_VCO_DIVIDER_2 && (ARCH_MPC832X || ARCH_MPC8360) + default 0 if QUICC_VCO_DIVIDER_4 && (ARCH_MPC832X || ARCH_MPC8360) + default 1 if QUICC_VCO_DIVIDER_8 && ARCH_MPC8360 + +config QUICC_DIV_FACTOR + int + default 0 if !MPC83XX_QUICC_ENGINE + default 0 if QUICC_DIV_FACTOR_1 + default 1 if QUICC_DIV_FACTOR_2 + +config QUICC_MULT_FACTOR + int + default 0 if !MPC83XX_QUICC_ENGINE + default 2 if QUICC_MULT_FACTOR_2 + default 3 if QUICC_MULT_FACTOR_3 + default 4 if QUICC_MULT_FACTOR_4 + default 5 if QUICC_MULT_FACTOR_5 + default 6 if QUICC_MULT_FACTOR_6 + default 7 if QUICC_MULT_FACTOR_7 + default 8 if QUICC_MULT_FACTOR_8 + default 9 if QUICC_MULT_FACTOR_9 + default 10 if QUICC_MULT_FACTOR_10 + default 11 if QUICC_MULT_FACTOR_11 + default 12 if QUICC_MULT_FACTOR_12 + default 13 if QUICC_MULT_FACTOR_13 + default 14 if QUICC_MULT_FACTOR_14 + default 15 if QUICC_MULT_FACTOR_15 + default 16 if QUICC_MULT_FACTOR_16 + default 17 if QUICC_MULT_FACTOR_17 + default 18 if QUICC_MULT_FACTOR_18 + default 19 if QUICC_MULT_FACTOR_19 + default 20 if QUICC_MULT_FACTOR_20 + default 21 if QUICC_MULT_FACTOR_21 + default 22 if QUICC_MULT_FACTOR_22 + default 23 if QUICC_MULT_FACTOR_23 + default 24 if QUICC_MULT_FACTOR_24 + default 25 if QUICC_MULT_FACTOR_25 + default 26 if QUICC_MULT_FACTOR_26 + default 27 if QUICC_MULT_FACTOR_27 + default 28 if QUICC_MULT_FACTOR_28 + default 29 if QUICC_MULT_FACTOR_29 + default 30 if QUICC_MULT_FACTOR_30 + default 31 if QUICC_MULT_FACTOR_31 + +config PCI_HOST_MODE + int + default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308 + default 0 if PCI_HOST_MODE_DISABLE + default 1 if PCI_HOST_MODE_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless + +config PCI_64BIT_MODE + int + default 0 if !ARCH_MPC8349 + default 0 if PCI_64BIT_MODE_DISABLE + default 1 if PCI_64BIT_MODE_ENABLE + +config PCI_INT_ARBITER1 + int + default 0 if !MPC83XX_PCI_SUPPORT && !ARCH_MPC8308 + default 0 if PCI_INT_ARBITER1_DISABLE + default 1 if PCI_INT_ARBITER1_ENABLE || ARCH_MPC8308 # MPC8308 needs this bit set regardless + +config PCI_INT_ARBITER2 + int + default 0 if !ARCH_MPC8349 + default 0 if PCI_INT_ARBITER2_DISABLE + default 1 if PCI_INT_ARBITER2_ENABLE + +config PCI_CLOCK_OUTPUT_DRIVE + int + default 0 if !ARCH_MPC8360 + default 0 if PCI_CLOCK_OUTPUT_DRIVE_DISABLE + default 1 if PCI_CLOCK_OUTPUT_DRIVE_ENABLE diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h new file mode 100644 index 0000000000..7d66ba726b --- /dev/null +++ b/arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h @@ -0,0 +1,37 @@ +#ifdef CONFIG_ARCH_MPC8349 +#define TSEC1_MODE_SHIFT 17 +#define TSEC2_MODE_SHIFT 19 +#else +#define TSEC1_MODE_SHIFT 18 +#define TSEC2_MODE_SHIFT 21 +#endif + +#define CONFIG_SYS_HRCW_LOW (\ + (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ + (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ + (CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\ + (CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\ + (CONFIG_CORE_PLL_RATIO << (31 - 15)) |\ + (CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\ + (CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\ + (CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \ + ) + +#define CONFIG_SYS_HRCW_HIGH (\ + (CONFIG_PCI_HOST_MODE << (31 - 0)) |\ + (CONFIG_PCI_64BIT_MODE << (31 - 1)) |\ + (CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\ + (CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\ + (CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\ + (CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\ + (CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\ + (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ + (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ + (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ + (CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ + (CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ + (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ + (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ + (CONFIG_LALE_TIMING << (31 - 29)) |\ + (CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \ + ) diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index a3bacf138c..8784445e15 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -24,6 +24,8 @@ #include <asm/mmu.h> #include <asm/u-boot.h>
+#include "hrcw/hrcw.h" + /* We don't want the MMU yet. */ #undef MSR_KERNEL diff --git a/board/freescale/mpc8315erdb/MAINTAINERS b/board/freescale/mpc8315erdb/MAINTAINERS index 5a67b40993..cdac1ac2ee 100644 --- a/board/freescale/mpc8315erdb/MAINTAINERS +++ b/board/freescale/mpc8315erdb/MAINTAINERS @@ -4,3 +4,4 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8315erdb/ F: include/configs/MPC8315ERDB.h F: configs/MPC8315ERDB_defconfig +F: configs/MPC8315ERDB_NANDSPL_defconfig diff --git a/board/freescale/mpc8349emds/MAINTAINERS b/board/freescale/mpc8349emds/MAINTAINERS index f236d543cc..25c5f5f95c 100644 --- a/board/freescale/mpc8349emds/MAINTAINERS +++ b/board/freescale/mpc8349emds/MAINTAINERS @@ -4,4 +4,5 @@ S: Orphan (since 2018-05) F: board/freescale/mpc8349emds/ F: include/configs/MPC8349EMDS.h F: configs/MPC8349EMDS_defconfig +F: configs/MPC8349EMDS_PCI64_defconfig F: configs/MPC8349EMDS_SLAVE_defconfig diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c index d90553384f..c4bec090be 100644 --- a/board/freescale/mpc8349itx/mpc8349itx.c +++ b/board/freescale/mpc8349itx/mpc8349itx.c @@ -19,6 +19,8 @@ #include <linux/libfdt.h> #endif
+#include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h" + DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SPD_EEPROM diff --git a/board/freescale/mpc837xemds/MAINTAINERS b/board/freescale/mpc837xemds/MAINTAINERS index 8386aa7297..ce9c446f2d 100644 --- a/board/freescale/mpc837xemds/MAINTAINERS +++ b/board/freescale/mpc837xemds/MAINTAINERS @@ -4,4 +4,5 @@ S: Orphan (since 2018-05) F: board/freescale/mpc837xemds/ F: include/configs/MPC837XEMDS.h F: configs/MPC837XEMDS_defconfig +F: configs/MPC837XEMDS_SLAVE_defconfig F: configs/MPC837XEMDS_HOST_defconfig diff --git a/configs/MPC8308RDB_defconfig b/configs/MPC8308RDB_defconfig index eaa30f4870..e4d6be2957 100644 --- a/configs/MPC8308RDB_defconfig +++ b/configs/MPC8308RDB_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308RDB=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/MPC8313ERDB_33_defconfig b/configs/MPC8313ERDB_33_defconfig index a893cd66f0..715640eecc 100644 --- a/configs/MPC8313ERDB_33_defconfig +++ b/configs/MPC8313ERDB_33_defconfig @@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_66_defconfig b/configs/MPC8313ERDB_66_defconfig index 4522cadc53..14e38a990e 100644 --- a/configs/MPC8313ERDB_66_defconfig +++ b/configs/MPC8313ERDB_66_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NOR=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8313ERDB_NAND_33_defconfig b/configs/MPC8313ERDB_NAND_33_defconfig index 3d74d718fa..08fa4ed817 100644 --- a/configs/MPC8313ERDB_NAND_33_defconfig +++ b/configs/MPC8313ERDB_NAND_33_defconfig @@ -5,6 +5,13 @@ CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_33MHZ" diff --git a/configs/MPC8313ERDB_NAND_66_defconfig b/configs/MPC8313ERDB_NAND_66_defconfig index 62c9f62d83..ac3a444222 100644 --- a/configs/MPC8313ERDB_NAND_66_defconfig +++ b/configs/MPC8313ERDB_NAND_66_defconfig @@ -5,6 +5,12 @@ CONFIG_SPL=y CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8313ERDB_NAND=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_66MHZ" diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig index 708a494554..078e4b2d02 100644 --- a/configs/MPC8315ERDB_defconfig +++ b/configs/MPC8315ERDB_defconfig @@ -3,6 +3,14 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8315ERDB=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8323ERDB_defconfig b/configs/MPC8323ERDB_defconfig index 272b070ec5..ff149f2e2e 100644 --- a/configs/MPC8323ERDB_defconfig +++ b/configs/MPC8323ERDB_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8323ERDB=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC832XEMDS_ATM_defconfig b/configs/MPC832XEMDS_ATM_defconfig index 68d5c46112..e8c8fd5528 100644 --- a/configs/MPC832XEMDS_ATM_defconfig +++ b/configs/MPC832XEMDS_ATM_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1" diff --git a/configs/MPC832XEMDS_HOST_33_defconfig b/configs/MPC832XEMDS_HOST_33_defconfig index 5db4a15734..6077e42b70 100644 --- a/configs/MPC832XEMDS_HOST_33_defconfig +++ b/configs/MPC832XEMDS_HOST_33_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_33M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_HOST_66_defconfig b/configs/MPC832XEMDS_HOST_66_defconfig index 15686600b4..9660d4d816 100644 --- a/configs/MPC832XEMDS_HOST_66_defconfig +++ b/configs/MPC832XEMDS_HOST_66_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI_66M,PQ_MDS_PIB=1" diff --git a/configs/MPC832XEMDS_SLAVE_defconfig b/configs/MPC832XEMDS_SLAVE_defconfig index ca9799cfe1..4810f7df69 100644 --- a/configs/MPC832XEMDS_SLAVE_defconfig +++ b/configs/MPC832XEMDS_SLAVE_defconfig @@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" diff --git a/configs/MPC832XEMDS_defconfig b/configs/MPC832XEMDS_defconfig index e9eec2f6cb..a84a778b3f 100644 --- a/configs/MPC832XEMDS_defconfig +++ b/configs/MPC832XEMDS_defconfig @@ -3,6 +3,12 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC832XEMDS=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349EMDS_PCI64_defconfig b/configs/MPC8349EMDS_PCI64_defconfig new file mode 100644 index 0000000000..22c91cbcf3 --- /dev/null +++ b/configs/MPC8349EMDS_PCI64_defconfig @@ -0,0 +1,32 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +# CONFIG_MMC is not set +CONFIG_MTD_NOR_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_SDRAM_defconfig b/configs/MPC8349EMDS_SDRAM_defconfig index ffb2850269..ed0f6e1d5e 100644 --- a/configs/MPC8349EMDS_SDRAM_defconfig +++ b/configs/MPC8349EMDS_SDRAM_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS_SDRAM=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349EMDS_SLAVE_defconfig b/configs/MPC8349EMDS_SLAVE_defconfig index a5f8686bda..5239ea3114 100644 --- a/configs/MPC8349EMDS_SLAVE_defconfig +++ b/configs/MPC8349EMDS_SLAVE_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y +CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" @@ -16,7 +25,8 @@ CONFIG_CMD_PING=y CONFIG_CMD_DATE=y # CONFIG_MMC is not set CONFIG_MTD_NOR_FLASH=y -CONFIG_PHYLIB=y +CONFIG_NETDEVICES=y +CONFIG_TSEC_ENET=y # CONFIG_PCI is not set CONFIG_SYS_NS16550=y CONFIG_OF_LIBFDT=y diff --git a/configs/MPC8349EMDS_defconfig b/configs/MPC8349EMDS_defconfig index da99227b79..ff5f2db6f7 100644 --- a/configs/MPC8349EMDS_defconfig +++ b/configs/MPC8349EMDS_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349EMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_ONE_PCI1=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/MPC8349ITXGP_defconfig b/configs/MPC8349ITXGP_defconfig index 589900449e..24e7d996f9 100644 --- a/configs/MPC8349ITXGP_defconfig +++ b/configs/MPC8349ITXGP_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFE000000" diff --git a/configs/MPC8349ITX_LOWBOOT_defconfig b/configs/MPC8349ITX_LOWBOOT_defconfig index 0d9d492963..4fa8aabb35 100644 --- a/configs/MPC8349ITX_LOWBOOT_defconfig +++ b/configs/MPC8349ITX_LOWBOOT_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8349ITX_defconfig b/configs/MPC8349ITX_defconfig index f194aec527..02ec242de7 100644 --- a/configs/MPC8349ITX_defconfig +++ b/configs/MPC8349ITX_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xFEF00000 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8349ITX=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_HOST_defconfig b/configs/MPC837XEMDS_HOST_defconfig index c0eb8289c0..44451ec48c 100644 --- a/configs/MPC837XEMDS_HOST_defconfig +++ b/configs/MPC837XEMDS_HOST_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XEMDS_SLAVE_defconfig b/configs/MPC837XEMDS_SLAVE_defconfig new file mode 100644 index 0000000000..afd8d42a97 --- /dev/null +++ b/configs/MPC837XEMDS_SLAVE_defconfig @@ -0,0 +1,33 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_MPC83xx=y +CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE" +CONFIG_BOOTDELAY=6 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_IMLS=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_DATE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_SYS_NS16550=y +CONFIG_OF_LIBFDT=y diff --git a/configs/MPC837XEMDS_defconfig b/configs/MPC837XEMDS_defconfig index 236f9f82ba..c85c962bf3 100644 --- a/configs/MPC837XEMDS_defconfig +++ b/configs/MPC837XEMDS_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XEMDS=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_6_1=y +CONFIG_CORE_PLL_RATIO_15_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig index b1a80dded9..757c850c42 100644 --- a/configs/MPC837XERDB_SLAVE_defconfig +++ b/configs/MPC837XERDB_SLAVE_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE,PCIE" diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index cdf67f9e4c..28c257e3aa 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=66666667 CONFIG_MPC83xx=y CONFIG_TARGET_MPC837XERDB=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_5_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCIE" diff --git a/configs/TQM834x_defconfig b/configs/TQM834x_defconfig index d576a207df..c5151b3dad 100644 --- a/configs/TQM834x_defconfig +++ b/configs/TQM834x_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0x80000000 CONFIG_SYS_CLK_FREQ=66666000 CONFIG_MPC83xx=y CONFIG_TARGET_TQM834X=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index acf3b6b44f..ae224d596b 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_CADDY2=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index b11a5c4cc1..2e9ff71990 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 050d5e3824..55e87dd03e 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -4,6 +4,12 @@ CONFIG_IDENT_STRING=" hrcon dh 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_HRCON=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index 1321509ac4..672e152ba5 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -3,6 +3,9 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_IDS8313=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_8BIT=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_IMAGE_FORMAT_LEGACY=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 21cf3ca18f..c192d556a4 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMCOGE5NE=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_VCO_DIV_4=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_6=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 00c24d1ad0..348524da8e 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -3,6 +3,15 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMETER1=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_VCO_DIV_4=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_6=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y +CONFIG_LDP_PIN_MUX_STATE_0=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 496bfc061f..9f8078cf49 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMOPTI2=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index bb3aa0e9bf..ce7f51668f 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMSUPX5=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index e0f3bb9096..b3d7981e11 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEGR1=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 82a1231486..d2812976f7 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMTEPR2=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/kmvect1_defconfig b/configs/kmvect1_defconfig index e2e1558513..57e416b34d 100644 --- a/configs/kmvect1_defconfig +++ b/configs/kmvect1_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_KMVECT1=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMVECT1" diff --git a/configs/mpc8308_p1m_defconfig b/configs/mpc8308_p1m_defconfig index 0ac5d5dc14..7b44bf26ed 100644 --- a/configs/mpc8308_p1m_defconfig +++ b/configs/mpc8308_p1m_defconfig @@ -3,6 +3,11 @@ CONFIG_SYS_TEXT_BASE=0xFC000000 CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_MPC8308_P1M=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 diff --git a/configs/sbc8349_PCI_33_defconfig b/configs/sbc8349_PCI_33_defconfig index 8101b6bdb7..1923f64bea 100644 --- a/configs/sbc8349_PCI_33_defconfig +++ b/configs/sbc8349_PCI_33_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=33000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_8_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_PCI_66_defconfig b/configs/sbc8349_PCI_66_defconfig index af3b37bfa0..2d0fac0f21 100644 --- a/configs/sbc8349_PCI_66_defconfig +++ b/configs/sbc8349_PCI_66_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/sbc8349_defconfig b/configs/sbc8349_defconfig index 6a1980b21f..65fbfb5103 100644 --- a/configs/sbc8349_defconfig +++ b/configs/sbc8349_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SBC8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_PCI_INT_ARBITER2_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 6e600ed77d..3866a6a2ef 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index afcd3c02ed..384ddaf2f9 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider con dp 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index 2c0069e999..ddbf4b522c 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 76e8f8ce38..dd96407e89 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -4,6 +4,11 @@ CONFIG_IDENT_STRING=" strider cpu dp 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_MPC83xx=y CONFIG_TARGET_STRIDER=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC2_MODE_RGMII=y CONFIG_CMD_IOLOOP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/suvd3_defconfig b/configs/suvd3_defconfig index 49426e651f..5a075d8fc5 100644 --- a/configs/suvd3_defconfig +++ b/configs/suvd3_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_SUVD3=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SUVD3" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index e7d309e7d2..2f8ec8bb1e 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUGE1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 857d8e1d52..a1bccb4bd8 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -3,6 +3,10 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_TUXX1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_QUICC_MULT_FACTOR_3=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y diff --git a/configs/ve8313_defconfig b/configs/ve8313_defconfig index e68e693dc2..c35f138440 100644 --- a/configs/ve8313_defconfig +++ b/configs/ve8313_defconfig @@ -3,6 +3,13 @@ CONFIG_SYS_TEXT_BASE=0xFE000000 CONFIG_SYS_CLK_FREQ=32000000 CONFIG_MPC83xx=y CONFIG_TARGET_VE8313=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_25_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_LALE_TIMING_EARLIER=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/vme8349_defconfig b/configs/vme8349_defconfig index 56c6e6dd94..bf2c350e16 100644 --- a/configs/vme8349_defconfig +++ b/configs/vme8349_defconfig @@ -3,6 +3,16 @@ CONFIG_SYS_TEXT_BASE=0xFFF00000 CONFIG_SYS_CLK_FREQ=66000000 CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y +CONFIG_DDR_MC_CLOCK_MODE_1_1=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_2_1=y +CONFIG_PCI_HOST_MODE_ENABLE=y +CONFIG_PCI_64BIT_MODE_ENABLE=y +CONFIG_PCI_INT_ARBITER1_ENABLE=y +CONFIG_BOOT_MEMORY_SPACE_LOW=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_GMII=y +CONFIG_TSEC2_MODE_GMII=y CONFIG_PCI_64BIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index c135b3c528..2ca7f771ad 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -27,38 +27,6 @@ #define CONFIG_TSEC1 #define CONFIG_VSC7385_ENET
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h index 6055cbd63f..e83428ce33 100644 --- a/include/configs/MPC8313ERDB_NAND.h +++ b/include/configs/MPC8313ERDB_NAND.h @@ -428,44 +428,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#ifdef CONFIG_SYS_66MHZ - -/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ -/* 0x62040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif defined(CONFIG_SYS_33MHZ) - -/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ -/* 0x65040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) -#endif - -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_ROM_LOC_NAND_SP_8BIT |\ - HRCWH_RL_EXT_NAND) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h index 29ea1a5b96..7eae2d0389 100644 --- a/include/configs/MPC8313ERDB_NOR.h +++ b/include/configs/MPC8313ERDB_NOR.h @@ -401,46 +401,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#ifdef CONFIG_SYS_66MHZ - -/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */ -/* 0x62040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#elif defined(CONFIG_SYS_33MHZ) - -/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */ -/* 0x65040000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#endif - -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
/* System IO Config */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 10a7a7b6ce..4a69565bc4 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -23,40 +23,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_3X1) -#define CONFIG_SYS_HRCW_HIGH_BASE (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) - -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_ROM_LOC_NAND_SP_8BIT |\ - HRCWH_RL_EXT_NAND) -#else -#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY) -#endif - /* * System IO Config */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c0bcdeac6b..d5353ffae7 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -15,30 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2_5X1 |\ - HRCWL_CE_PLL_VCO_DIV_2 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) - /* * System IO Config */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 6f75909293..97a2d93d8d 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -12,43 +12,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1 |\ - HRCWL_CE_PLL_VCO_DIV_2 |\ - HRCWL_CE_PLL_DIV_1X1 |\ - HRCWL_CE_TO_PLL_1X3) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LALE_NORMAL) -#endif - /* * System IO Config */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 2696dfd748..9128663dba 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -17,12 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#elif CONFIG_SYS_CLK_FREQ == 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -367,86 +361,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif /* CONFIG_PCI_64BIT */ -#endif /* CONFIG_PCISLAVE */ - /* * System performance */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h index 6d0ee81746..2f69a1812d 100644 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ b/include/configs/MPC8349EMDS_SDRAM.h @@ -17,12 +17,6 @@ */ #define CONFIG_E300 1 /* E300 Family */
-#if CONFIG_SYS_CLK_FREQ == 66000000 || CONFIG_SYS_CLK_FREQ == 66666666 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#elif CONFIG_SYS_CLK_FREQ == 33000000 -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -439,86 +433,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif /* CONFIG_PCI_64BIT */ -#endif /* CONFIG_PCISLAVE */ - /* * System performance */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 402e0d297d..293b7432e4 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -39,10 +39,6 @@ #ifndef __CONFIG_H #define __CONFIG_H
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) -#define CONFIG_SYS_LOWBOOT -#endif - /* * High Level Configuration Options */ @@ -465,41 +461,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_SYS_LOWBOOT -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* * System performance */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 5148bcf994..568cdfd527 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -12,48 +12,6 @@ */ #define CONFIG_E300 1 /* E300 family */
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66MHz, then - * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_6X1 |\ - HRCWL_CORE_TO_CSB_1_5X1) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#endif - /* Arbiter Configuration Register */ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 7ad0cf5c33..19b9a654c6 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -20,46 +20,6 @@ */ #define CONFIG_VSC7385_ENET
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#endif - /* System performance - define the value i.e. CONFIG_SYS_XXX */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 68f6d66e0f..a15d77a7b5 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -263,41 +263,6 @@ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h index 08a9c06059..f256ce8b27 100644 --- a/include/configs/caddy2.h +++ b/include/configs/caddy2.h @@ -25,12 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#ifdef CONFIG_PCI_66M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -293,41 +287,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 552826c2b1..b54a34f5e2 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -16,38 +16,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 2813b74872..87ed565770 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -25,27 +25,6 @@ #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.000MHz, then - * CSB = 132MHz, CORE = 264MHz, DDRC = 264MHz, LBC = 132MHz - */ -#define CONFIG_SYS_HRCW_LOW (0x20000000 /* reserved, must be set */ |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_CSB_TO_CLKIN_2X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_8BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_MII |\ - HRCWH_BIG_ENDIAN) - #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D)
diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index 87efaa4a7c..e2cdaad446 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -322,25 +322,6 @@ */ #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X6) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY | \ - HRCWH_LDP_CLEAR) - /** * DDR RAM settings */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index ac636b7e21..73d2da90e5 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -308,25 +308,6 @@ */ #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X6) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY | \ - HRCWH_LDP_CLEAR) - /** * DDR RAM settings */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h index 60f7fd09d9..f7998cc171 100644 --- a/include/configs/kmopti2.h +++ b/include/configs/kmopti2.h @@ -327,28 +327,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index 4af2903ec2..0ee2faf305 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -327,28 +327,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h index c731c0666f..1229e4c28f 100644 --- a/include/configs/kmtegr1.h +++ b/include/configs/kmtegr1.h @@ -378,28 +378,6 @@ #define CONFIG_SYS_GP2DIR 0xFF000000 #define CONFIG_SYS_GP2ODR 0x00000000
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h index ca7a1477e2..a37e3997a0 100644 --- a/include/configs/kmtepr2.h +++ b/include/configs/kmtepr2.h @@ -327,28 +327,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/kmvect1.h b/include/configs/kmvect1.h index 9eae4cdf07..a9561e1a67 100644 --- a/include/configs/kmvect1.h +++ b/include/configs/kmvect1.h @@ -370,28 +370,6 @@ #define CONFIG_SYS_GP2DIR 0xFF000000 #define CONFIG_SYS_GP2ODR 0x00000000
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 5613d3b335..d665a3ee11 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -21,38 +21,6 @@ #define CONFIG_TSEC1 #define CONFIG_TSEC2
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_MII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 1f7bfd63a7..10f3cbfb23 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -22,12 +22,6 @@ /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#ifdef CONFIG_PCI_33M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#else /* 66M */ -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -377,71 +371,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#if 1 /*528/264*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*396/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_3X1) -#elif 0 /*264/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_2X1) -#elif 0 /*132/132*/ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#elif 0 /*264/264 */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X4 |\ - HRCWL_CORE_TO_CSB_1X1) -#endif - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A diff --git a/include/configs/strider.h b/include/configs/strider.h index 48cbbdaace..f44b47fbbe 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -16,38 +16,6 @@
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
-/* - * Hardware Reset Configuration Word - * if CLKIN is 66.66MHz, then - * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz - * We choose the A type silicon as default, so the core is 400Mhz. - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_2X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_4X1 |\ - HRCWL_CORE_TO_CSB_3X1) -/* - * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits - * in 8308's HRCWH according to the manual, but original Freescale's - * code has them and I've expirienced some problems using the board - * with BDI3000 attached when I've tried to set these bits to zero - * (UART doesn't work after the 'reset run' command). - */ -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_MII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN) - /* * System IO Config */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index a652343d95..b4e624347a 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -324,28 +324,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h index cfd317f6e1..98a78b810a 100644 --- a/include/configs/tuge1.h +++ b/include/configs/tuge1.h @@ -327,28 +327,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index b3bfb7b7c5..954c71e279 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -327,28 +327,6 @@ */ #define CONFIG_SYS_SICRL SICRL_IRQ_CKS
-/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \ - HRCWL_DDR_TO_SCB_CLK_2X1 | \ - HRCWL_CSB_TO_CLKIN_2X1 | \ - HRCWL_CORE_TO_CSB_2_5X1 | \ - HRCWL_CE_PLL_VCO_DIV_2 | \ - HRCWL_CE_TO_PLL_1X3) - -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT | \ - HRCWH_PCI_ARBITER_DISABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE | \ - HRCWH_SW_WATCHDOG_DISABLE | \ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_NORMAL) - #define CONFIG_SYS_DDRCDR (\ DDRCDR_EN | \ DDRCDR_PZ_MAXZ | \ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index b08a8eb116..05529afca2 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -311,25 +311,6 @@ /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-/* 0x64050000 */ -#define CONFIG_SYS_HRCW_LOW (\ - 0x20000000 /* reserved, must be set */ |\ - HRCWL_DDRCM |\ - HRCWL_CSB_TO_CLKIN_4X1 | \ - HRCWL_CORE_TO_CSB_2_5X1) - -/* 0xa0600004 */ -#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \ - HRCWH_PCI_ARBITER_ENABLE | \ - HRCWH_CORE_ENABLE | \ - HRCWH_FROM_0X00000100 | \ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT | \ - HRCWH_TSEC1M_IN_MII | \ - HRCWH_BIG_ENDIAN | \ - HRCWH_LALE_EARLY) - /* System IO Config */ #define CONFIG_SYS_SICRH (0x01000000 | \ SICRH_ETSEC2_B | \ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index ee84d09791..b3bfe39df6 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -25,14 +25,6 @@ /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
-#define CONFIG_PCI_66M - -#ifdef CONFIG_PCI_66M -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 -#else -#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 -#endif - #define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ @@ -295,41 +287,6 @@
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_CSB_TO_CLKIN |\ - HRCWL_VCO_1X2 |\ - HRCWL_CORE_TO_CSB_2X1) - -#if defined(CONFIG_PCI_64BIT) -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_64_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_32_BIT_PCI |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_PCI2_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_TSEC1M_IN_GMII |\ - HRCWH_TSEC2M_IN_GMII) -#endif - /* System IO Config */ #define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A