IXP465 cpu support

This adds support for the intel IXP465 cpu including ECC. The new
common initialisation was also tested on IXP425.
Derived from a work by Michael Trimarchi but heavily modified.

Signed-off-by: Hendrik Sattler

---
 cpu/ixp/cpu.c                       |   85 ++++
 cpu/ixp/interrupts.c                |    5 
 cpu/ixp/npe/npe.c                   |    2 
 cpu/ixp/pci.c                       |    2 
 cpu/ixp/serial.c                    |   30 -
 cpu/ixp/start.S                     |  259 +++++++++++----
 cpu/ixp/timer.c                     |    2 
 drivers/pci/pci.c                   |    8 
 include/asm-arm/arch-ixp/hardware.h |   24 +
 include/asm-arm/arch-ixp/ixp425.h   |   82 +++-
 include/asm-arm/arch-ixp/ixp465.h   |  614 ++++++++++++++++++++++++++++++++++++
 11 files changed, 989 insertions(+), 124 deletions(-)

--- u-boot-1.3.4.orig/cpu/ixp/cpu.c
+++ u-boot-1.3.4/cpu/ixp/cpu.c
@@ -7,6 +7,10 @@
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Alex Zuepke <azu@sysgo.de>
  *
+ * (C) Copyright 2008
+ * Erhardt+Leimer, GmbH <www.erhardt-leimer.com>
+ * Hendrik Sattler <hendrik.sattler@mixed-mode.de>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -32,7 +36,10 @@
 
 #include <common.h>
 #include <command.h>
-#include <asm/arch/ixp425.h>
+#include <asm/arch/hardware.h>
+
+#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
+#define REG_READ(b,o,v)	 ((v)=(*(volatile unsigned int*)((b+o))))
 
 ulong loops_per_jiffy;
 
@@ -44,32 +51,90 @@
 int print_cpuinfo (void)
 {
 	unsigned long id;
-	int speed = 0;
+	unsigned long speed_cfg = 0;
+	unsigned long speed = 0;
+	unsigned int type = 0;
 
 	asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id));
-
-	puts("CPU:   Intel IXP425 at ");
 	switch ((id & 0x000003f0) >> 4) {
+#ifdef CONFIG_IXP425
 	case 0x1c:
-		loops_per_jiffy = 887467;
+		type = 425;
 		speed = 533;
 		break;
 
 	case 0x1d:
-		loops_per_jiffy = 666016;
+		type = 425;
 		speed = 400;
 		break;
 
 	case 0x1f:
-		loops_per_jiffy = 442901;
+		type = 425;
 		speed = 266;
 		break;
+#endif
+#ifdef CONFIG_IXP465
+	case 0x20:
+		type = 465;
+		//the current speed setting
+		REG_READ(IXP425_EXP_CFG_BASE_PHYS, IXP425_EXP_CFG0_OFFSET, speed_cfg);
+		//read factory speed
+		REG_READ(IXP425_EXP_CFG_BASE_PHYS, IXP425_EXP_CFG2_OFFSET, speed);
+		switch (speed) {
+		default:
+			if (speed_cfg & (1 << 23) || ((speed_cfg >> 21) & 0x3) == 0) {
+				speed = 667;
+				break;
+			}
+
+		case 0:
+			if (speed_cfg & (1 << 23) || ((speed_cfg >> 21) & 0x3) <= 1) {
+				speed = 533;
+				break;
+			}
+
+		case 1:
+			if (speed_cfg & (1 << 23) || ((speed_cfg >> 21) & 0x3) != 2) {
+				speed = 400;
+				break;
+			}
+
+		case 3:
+			speed = 266;
+			break;
+
+		}
+		break;
+#endif
 	}
 
-	if (speed)
-		printf("%d MHz\n", speed);
+	if (type)
+		printf("CPU:   Intel IXP%u", type);
 	else
-		puts("unknown revision\n");
+		puts("CPU:   Unknown CPU");
+
+	if (speed) {
+		printf(" @ %lu MHz\n", speed);
+		switch (speed) {
+		case 266:
+			loops_per_jiffy = 442901;
+			break;
+
+		case 400:
+			loops_per_jiffy = 666016;
+			break;
+
+		case 533:
+			loops_per_jiffy = 887467;
+			break;
+
+		default:
+			/* not exact */
+			loops_per_jiffy = 222000 * (speed/133);
+			break;
+		}
+	} else
+		puts(", unknown revision\n");
 
 	return 0;
 }
--- u-boot-1.3.4.orig/cpu/ixp/interrupts.c
+++ u-boot-1.3.4/cpu/ixp/interrupts.c
@@ -30,7 +30,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/ixp425.h>
+#include <asm/arch/hardware.h>
 
 #ifdef CONFIG_USE_IRQ
 #include <asm/proc-armv/ptrace.h>
--- u-boot-1.3.4.orig/cpu/ixp/npe/npe.c
+++ u-boot-1.3.4/cpu/ixp/npe/npe.c
@@ -31,7 +31,7 @@
 #include <miiphy.h>
 #include <malloc.h>
 #include <asm/processor.h>
-#include <asm/arch-ixp/ixp425.h>
+#include <asm/arch/hardware.h>
 
 #include <IxOsal.h>
 #include <IxEthAcc.h>
--- u-boot-1.3.4.orig/cpu/ixp/pci.c
+++ u-boot-1.3.4/cpu/ixp/pci.c
@@ -30,7 +30,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 #include <pci.h>
-#include <asm/arch/ixp425.h>
+#include <asm/arch/hardware.h>
 #include <asm/arch/ixp425pci.h>
 
 static void non_prefetch_read (unsigned int addr, unsigned int cmd,
--- u-boot-1.3.4.orig/cpu/ixp/serial.c
+++ u-boot-1.3.4/cpu/ixp/serial.c
@@ -29,7 +29,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/ixp425.h>
+#include <asm/arch/hardware.h>
 
 /*
  *               14.7456 MHz
--- u-boot-1.3.4.orig/cpu/ixp/start.S
+++ u-boot-1.3.4/cpu/ixp/start.S
@@ -29,7 +29,8 @@
 
 #include <config.h>
 #include <version.h>
-#include <asm/arch/ixp425.h>
+
+#include <asm/arch/hardware.h>
 
 #define MMU_Control_M  0x001    /* Enable MMU */
 #define MMU_Control_A  0x002    /* Enable address alignment faults */
@@ -123,48 +124,110 @@
 	.word 0x0badc0de
 #endif
 
-/****************************************************************************/
-/*									    */
-/* the actual reset code						    */
-/*									    */
-/****************************************************************************/
-
-reset:
-	/* disable mmu, set big-endian */
-	mov	r0, #0xf8
-	mcr	p15, 0, r0, c1, c0, 0
-	CPWAIT  r0
-
-	/* invalidate I & D caches & BTB */
-	mcr	p15, 0, r0, c7, c7, 0
-	CPWAIT	r0
-
-	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
-	CPWAIT r0
-
-	/* drain write and fill buffers */
-	mcr	p15, 0, r0, c7, c10, 4
-	CPWAIT	r0
+/* (DDR-)SDRAM memory initialisation code */
+.globl memory_init
+memory_init:
+#if defined(CONFIG_IXP465)
+	/* Setup SDRAM controller */
+	ldr     r0, =IXP_DDR_CFG_BASE1
+
+	/* set DDR-SDRAM timings */
+	ldr     r1, =CFG_DDR_SDCR0_INIT
+	str     r1, [r0, #IXP_DDR_SDCR0]
+
+	ldr     r1, =CFG_DDR_SDCR1_INIT
+	str     r1, [r0, #IXP_DDR_SDCR1]
+
+	/* set DDR-SDRAM layout */
+	mov     r1, #IXP425_SDRAM_BASE
+	str     r1, [r0, #IXP_DDR_SDBR]
+	ldr     r1, [r0, #IXP_DDR_SDBR]
+
+	ldr     r1, =CFG_DDR_SBR0_INIT
+	str     r1, [r0, #IXP_DDR_SBR0]
+	ldr     r1, [r0, #IXP_DDR_SBR0]
+
+	ldr     r1, =CFG_DDR_SBR1_INIT
+	str     r1, [r0, #IXP_DDR_SBR1]
+	ldr     r1, [r0, #IXP_DDR_SBR1]
+
+#if defined(CONFIG_SDRAM_ECC) || defined(CONFIG_DDR_ECC)
+	/* enable ECC */
+	mov	r1, #0xe
+	str	r1, [r0, #IXP_DDR_ECCR]
+#else
+	/* disable ECC */
+	mov	r1, #0
+	str	r1, [r0, #IXP_DDR_ECCR]
+#endif
 
-	/* disable write buffer coalescing */
-	mrc	p15, 0, r0, c1, c0, 1
-	orr	r0, r0, #1
-	mcr	p15, 0, r0, c1, c0, 1
-	CPWAIT	r0
+	/* 11.2.2.8 DDRI SDR Initialisation */
+	/* Step 1-4 performed by MCU */
 
-	/* set EXP CS0 to the optimum timing */
-	ldr	r1, =CFG_EXP_CS0
-	ldr     r2, =IXP425_EXP_CS0
-	str     r1, [r2]
+	ldr     r0, =IXP_DDR_CFG_BASE2
+	/* Step 5. Overwrite default value */
+	ldr	r1, =(0x00001000)
+	str	r1, [r0, #IXP_DDR_RCOMP_CSR3]
+
+	/* Step 6. Overwrite default value */
+	ldr	r1, =(0x000208F0)
+	str	r1, [r0, #IXP_DDR_DRIVE3]
+
+	ldr     r0, =IXP_DDR_CFG_BASE1
+	/* Step 7. Disable refresh cycles */
+	mov     r1, #0
+	str     r1, [r0, #IXP_DDR_RFR]
+
+	/* Step 8. Send NOP command */
+	mov     r1, #DDR_SDIR_NOP
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x100000, r1
+
+	/* Step 9. Issue precharge-all command to close all open banks */
+	mov     r1, #DDR_SDIR_PRECHARGE_ALL
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x100000, r1
+
+	/* Step 10. Issue extended mode register set to enable dll */
+	mov     r1, #DDR_SDIR_EMRS_DLL_ENABLE
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x100000, r1
+
+	/* Step 11. Issue mode register set w/ DLL reset */
+	mov     r1, #DDR_SDIR_MODE_SET_RESET
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x100000, r1
+
+	/* Step 12. Issue precharge-all command */
+	mov     r1, #DDR_SDIR_PRECHARGE_ALL
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x100000, r1
+
+	/* Step 13. provide 2 auto-refresh cycles */
+	mov     r1, #DDR_SDIR_AUTO_REFRESH
+	mov     r2, #2
+3:
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x800, r3
+	subs    r2, r2, #1
+	bne     3b
+
+	/* Step 14. Issue mode register set w/o DLL reset */
+	mov     r1, #DDR_SDIR_MODE_SET_NO_RESET
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x100000, r1
+
+	/* Step 15. start normal operation */
+	mov     r1, #0xf
+	str     r1, [r0, #IXP_DDR_SDIR]
+	DELAY_FOR 0x10000, r1
+
+	/* Step 16. Set refresh val to 7.8us, see 11.2.2.12 */
+	ldr     r1, =CFG_SDRAM_REFRESH_CNT
+	str     r1, [r0, #IXP_DDR_RFR]
+	DELAY_FOR 0x100000, r1
 
-	/* make sure flash is visible at 0 */
-#if 0
-	ldr	r2, =IXP425_EXP_CFG0
-	ldr     r1, [r2]
-	orr     r1, r1, #0x80000000
-	str     r1, [r2]
-#endif
+#elif defined(CONFIG_IXP425)
 	mov	r1, #CFG_SDR_CONFIG
 	ldr     r2, =IXP425_SDR_CONFIG
 	str     r1, [r2]
@@ -207,44 +270,111 @@
 	mov	r1, #6
 	str	r1, [r4]
 	DELAY_FOR 0x4000, r0
+#endif
+	/* everything is fine now */
+	mov   pc, lr
+
+/****************************************************************************/
+/*									    */
+/* the actual reset code						    */
+/*									    */
+/****************************************************************************/
 
-	/* copy */
-	mov     r0, #0
-	mov     r4, r0
-	add     r2, r0, #CFG_MONITOR_LEN
-	mov     r1, #0x10000000
-	mov     r5, r1
-
-    30:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r0, r2
-	bne     30b
+reset:
+	/* disable mmu, set big-endian */
+	mov	r0, #0xf8
+	mcr	p15, 0, r0, c1, c0, 0
+	CPWAIT  r0
 
 	/* invalidate I & D caches & BTB */
 	mcr	p15, 0, r0, c7, c7, 0
 	CPWAIT	r0
 
 	/* invalidate I & Data TLB */
-	mcr	p15, 0, r0, c8, c7, 0
+	mcr 	p15, 0, r0, c8, c7, 0
 	CPWAIT r0
 
 	/* drain write and fill buffers */
 	mcr	p15, 0, r0, c7, c10, 4
 	CPWAIT	r0
 
-	/* move flash to 0x50000000 */
+	/* disable write buffer coalescing */
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #1
+	mcr	p15, 0, r0, c1, c0, 1
+	CPWAIT	r0
+
+	/* set EXP CS0 to the optimum timing */
+	ldr	r1, =CFG_EXP_CS0
+	ldr     r2, =IXP425_EXP_CS0
+	str     r1, [r2]
+
+	/* setting up the memory */
+	mov   ip, lr
+	bl memory_init
+
+	/* calculate new program counter value */
+	ldr	r0, =2f
+	add	r0, r0, #CFG_FLASH_BASE
+	ldr	r3, _TEXT_BASE
+	sub	r0, r0, r3
+
+	/* move flash to 0x5000000 */
 	ldr	r2, =IXP425_EXP_CFG0
 	ldr     r1, [r2]
 	bic     r1, r1, #0x80000000
-	str     r1, [r2]
 
+	mov	r4, pc
+	cmp	r4, r3
+	bge	2f
+	ldr	r4, =0
+	b	1f
+	.p2align 5
+1:
+	/* if you debug this, jump to the value of $r0 */
+	str     r1, [r2]
 	nop
 	nop
 	nop
 	nop
+	mov	pc, r0
 	nop
-	nop
+2:
+
+#if defined(CONFIG_IXP465)
+#if ! defined(CONFIG_IXP425_COMPAT)
+	/* Route DDR transfers through MPI port
+	 * Enable P-attribute triggered byte swap (data coherency)
+	 */
+	ldr	r0, =IXP425_EXP_CFG1
+	ldr	r1, [r0]
+	ldr	r2, =(0x80000100)
+	orr	r1, r1, r2
+	str	r1, [r0]
+#endif
+#if defined(CONFIG_SDRAM_ECC) || defined(CONFIG_DDR_ECC)
+	/* flush memory to initialize ECC */
+	mov	r0, #CFG_SDRAM_BASE                    /* start */
+	ldr	r1, =(CFG_SDRAM_BASE + CFG_SDRAM_SIZE) /* end */
+	mov	r2, #0                                 /* init value */
+4:
+	str	r2, [r0], #4
+	cmp	r0, r1
+	blt	4b
+#endif
+#endif
+
+	/* invalidate I & D caches & BTB */
+	mcr	p15, 0, r0, c7, c7, 0
+	CPWAIT	r0
+
+	/* invalidate I & Data TLB */
+	mcr	p15, 0, r0, c8, c7, 0
+	CPWAIT r0
+
+	/* drain write and fill buffers */
+	mcr	p15, 0, r0, c7, c10, 4
+	CPWAIT	r0
 
 	/* invalidate I & Data TLB */
 	mcr	p15, 0, r0, c8, c7, 0
@@ -256,18 +386,19 @@
 	mcr     p15, 0, r0, c1, c0, 0
 	CPWAIT  r0
 
-	mrs	r0,cpsr			/* set the cpu to SVC32 mode	    */
-	bic	r0,r0,#0x1f		/* (superviser mode, M=10011)	    */
-	orr	r0,r0,#0x13
-	msr	cpsr,r0
+	mrs	r0, cpsr		/* set the cpu to SVC32 mode	    */
+	bic	r0, r0, #0x1f		/* (superviser mode, M=10011)	    */
+	orr	r0, r0, #0x13
+	msr	cpsr, r0
+
+	ldr	r1, =0
+	cmp     r4, r1			/* don't reloc during debug         */
+	bne     stack_setup
 
 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
 relocate:				/* relocate U-Boot to RAM	    */
-	adr	r0, _start		/* r0 <- current position of code   */
+	ldr 	r0, =CFG_FLASH_BASE	/* r0 <- position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
-
 	ldr	r2, _armboot_start
 	ldr	r3, _bss_start
 	sub	r2, r3, r2		/* r2 <- size of armboot            */
--- u-boot-1.3.4.orig/cpu/ixp/timer.c
+++ u-boot-1.3.4/cpu/ixp/timer.c
@@ -30,7 +30,7 @@
  */
 
 #include <common.h>
-#include <asm/arch/ixp425.h>
+#include <asm/arch/hardware.h>
 
 #ifndef CONFIG_USE_IRQ
 ulong get_timer (ulong base)
--- u-boot-1.3.4.orig/drivers/pci/pci.c
+++ u-boot-1.3.4/drivers/pci/pci.c
@@ -52,7 +52,7 @@
 PCI_HOSE_OP(write, word, u16)
 PCI_HOSE_OP(write, dword, u32)
 
-#ifndef CONFIG_IXP425
+#if !defined(CONFIG_IXP425) && !defined(CONFIG_IXP465)
 #define PCI_OP(rw, size, type, error_code)				\
 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)	\
 {									\
@@ -73,7 +73,7 @@
 PCI_OP(write, byte, u8, )
 PCI_OP(write, word, u16, )
 PCI_OP(write, dword, u32, )
-#endif	/* CONFIG_IXP425 */
+#endif	/* CONFIG_IXP425 and CONFIG_IXP465*/
 
 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)			\
 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
@@ -148,7 +148,7 @@
 	return NULL;
 }
 
-#ifndef CONFIG_IXP425
+#if !defined(CONFIG_IXP425) && !defined(CONFIG_IXP465)
 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 {
 	struct pci_controller * hose;
@@ -204,7 +204,7 @@
 
 	return (-1);
 }
-#endif	/* CONFIG_IXP425 */
+#endif	/* CONFIG_IXP425 and CONFIG_IXP465*/
 
 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 {
--- /dev/null
+++ u-boot-1.3.4/include/asm-arm/arch-ixp/hardware.h
@@ -0,0 +1,24 @@
+/*
+ * include/asm-arm/arch-ixp/hardware.h
+ *
+ *  Copyright (C) 2008 Michael Trimarchi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#if defined(CONFIG_IXP425)
+#include <asm/arch/ixp425.h>
+#elif defined(CONFIG_IXP465)
+#include <asm/arch/ixp465.h>
+#else
+#error "Unsupported IXP processor"
+#endif
+
+#endif
--- /dev/null
+++ u-boot-1.3.4/include/asm-arm/arch-ixp/ixp465.h
@@ -0,0 +1,614 @@
+/*
+ * include/asm-arm/arch-ixp/ixp465.h
+ *
+ * Register definitions for IXP465
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ASM_ARM_IXP465_H_
+#define _ASM_ARM_IXP465_H_
+
+#define BIT(x)	(1<<(x))
+
+/* FIXME: Only this does work for u-boot... find out why... [RS] */
+#define UBOOT_REG_FIX 1
+#ifdef UBOOT_REG_FIX
+# undef	io_p2v
+# undef __REG
+# ifndef __ASSEMBLY__
+#  define io_p2v(PhAdd)    (PhAdd)
+#  define __REG(x)	((volatile u32 *)io_p2v(x))
+# else
+#  define __REG(x) (x)
+#  define REG32(a, b) (b)
+# endif
+#endif /* UBOOT_REG_FIX */
+
+/*
+ * SDRAM
+ */
+#define IXP425_SDRAM_BASE		(0x00000000)
+
+/*
+ * PCI Configuration space
+ */
+#define IXP425_PCI_CFG_BASE_PHYS	(0xC0000000)
+#define IXP425_PCI_CFG_BASE_VIRT	(0xFFFD0000)
+#define IXP425_PCI_CFG_REGION_SIZE	(0x00001000)
+
+/*
+ * Expansion BUS Configuration registers
+ */
+#define IXP425_EXP_CFG_BASE_PHYS	(0xC4000000)
+#define IXP425_EXP_CFG_BASE_VIRT	(0xFFFD1000)
+#define IXP425_EXP_CFG_REGION_SIZE	(0x00001000)
+
+/*
+ * Peripheral space
+ */
+#define IXP425_PERIPHERAL_BASE_PHYS	(0xC8000000)
+#define IXP425_PERIPHERAL_BASE_VIRT	(0xFFFD2000)
+#define IXP425_PERIPHERAL_REGION_SIZE	(0x0000C000)
+
+/*
+ * SDRAM configuration registers
+ */
+
+#define IXP425_SDRAM_CFG_BASE_PHYS	(0xCC000000)
+
+#define IXP_DDR_CFG_BASE1       (0xCC00E500)
+#define IXP_DDR_CFG_BASE2       (0xCC00F500)
+
+#define IXP_DDR_SDIR           REG32(IXP_DDR_CFG_BASE1, 0x00)
+#define IXP_DDR_SDCR0          REG32(IXP_DDR_CFG_BASE1, 0x04)
+#define IXP_DDR_SDCR1          REG32(IXP_DDR_CFG_BASE1, 0x08)
+#define IXP_DDR_SDBR           REG32(IXP_DDR_CFG_BASE1, 0x0C)
+#define IXP_DDR_SBR0           REG32(IXP_DDR_CFG_BASE1, 0x10)
+#define IXP_DDR_SBR1           REG32(IXP_DDR_CFG_BASE1, 0x14)
+#define IXP_DDR_S32SR          REG32(IXP_DDR_CFG_BASE1, 0x18)
+#define IXP_DDR_ECCR           REG32(IXP_DDR_CFG_BASE1, 0x1C)
+#define IXP_DDR_ELOG0          REG32(IXP_DDR_CFG_BASE1, 0x20)
+#define IXP_DDR_ELOG1          REG32(IXP_DDR_CFG_BASE1, 0x24)
+#define IXP_DDR_ECAR0          REG32(IXP_DDR_CFG_BASE1, 0x28)
+#define IXP_DDR_ECAR1          REG32(IXP_DDR_CFG_BASE1, 0x2C)
+#define IXP_DDR_ECTST          REG32(IXP_DDR_CFG_BASE1, 0x30)
+#define IXP_DDR_MCISR          REG32(IXP_DDR_CFG_BASE1, 0x34)
+#define IXP_DDR_MACR           REG32(IXP_DDR_CFG_BASE1, 0x38)
+#define IXP_DDR_MPTCR          REG32(IXP_DDR_CFG_BASE1, 0x3C)
+#define IXP_DDR_MPCR           REG32(IXP_DDR_CFG_BASE1, 0x40)
+#define IXP_DDR_RFR            REG32(IXP_DDR_CFG_BASE1, 0x48)
+#define IXP_DDR_SDPR0          REG32(IXP_DDR_CFG_BASE1, 0x50)
+#define IXP_DDR_SDPR1          REG32(IXP_DDR_CFG_BASE1, 0x54)
+#define IXP_DDR_SDPR2          REG32(IXP_DDR_CFG_BASE1, 0x58)
+#define IXP_DDR_SDPR3          REG32(IXP_DDR_CFG_BASE1, 0x5C)
+#define IXP_DDR_SDPR4          REG32(IXP_DDR_CFG_BASE1, 0x60)
+#define IXP_DDR_SDPR5          REG32(IXP_DDR_CFG_BASE1, 0x64)
+#define IXP_DDR_SDPR6          REG32(IXP_DDR_CFG_BASE1, 0x68)
+#define IXP_DDR_SDPR7          REG32(IXP_DDR_CFG_BASE1, 0x6C)
+
+#define IXP_DDR_RCOMP_CSR3     REG32(IXP_DDR_CFG_BASE2, 0x70)
+#define IXP_DDR_DRIVE3         REG32(IXP_DDR_CFG_BASE2, 0xAC)
+
+/* SDIR command values */
+#define DDR_SDIR_MODE_SET_NO_RESET 0
+#define DDR_SDIR_MODE_SET_RESET    1
+#define DDR_SDIR_PRECHARGE_ALL     2
+#define DDR_SDIR_NOP               3
+#define DDR_SDIR_EMRS_DLL_ENABLE   4
+#define DDR_SDIR_EMRS_DLL_DISABLE  5
+#define DDR_SDIR_AUTO_REFRESH      6
+
+#define DDR_SBR_128Mx8  0
+#define DDR_SBR_128Mx16 0
+#define DDR_SBR_256Mx8  0
+#define DDR_SBR_256Mx16 (2 << 30)
+#define DDR_SBR_512Mx8  0
+#define DDR_SBR_512Mx16 0
+#define DDR_SBR_1Gx8    (3 << 30)
+#define DDR_SBR(x)     (((x) >> 24) & 0x7F)
+
+/*
+ * Q Manager space .. not static mapped
+ */
+#define IXP425_QMGR_BASE_PHYS		(0x60000000)
+#define IXP425_QMGR_BASE_VIRT		(0xFFFDE000)
+#define IXP425_QMGR_REGION_SIZE		(0x00004000)
+
+/*
+ * Expansion BUS
+ *
+ * Expansion Bus 'lives' at either base1 or base 2 depending on the value of
+ * Exp Bus config registers:
+ *
+ * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero,
+ * and The expansion bus to IXP425_EXP_BUS_BASE2
+ */
+#define IXP425_EXP_BUS_BASE1_PHYS	(0x00000000)
+#define IXP425_EXP_BUS_BASE2_PHYS	(0x50000000)
+#define IXP425_EXP_BUS_BASE2_VIRT	(0xF0000000)
+
+#define IXP425_EXP_BUS_BASE_PHYS	IXP425_EXP_BUS_BASE2_PHYS
+#define IXP425_EXP_BUS_BASE_VIRT	IXP425_EXP_BUS_BASE2_VIRT
+
+#define IXP425_EXP_BUS_REGION_SIZE	(0x08000000)
+#define IXP425_EXP_BUS_CSX_REGION_SIZE	(0x01000000)
+
+#define IXP425_EXP_BUS_CS0_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x00000000)
+#define IXP425_EXP_BUS_CS1_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x01000000)
+#define IXP425_EXP_BUS_CS2_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x02000000)
+#define IXP425_EXP_BUS_CS3_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x03000000)
+#define IXP425_EXP_BUS_CS4_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x04000000)
+#define IXP425_EXP_BUS_CS5_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x05000000)
+#define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
+#define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
+
+#define IXP425_EXP_BUS_CS0_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x00000000)
+#define IXP425_EXP_BUS_CS1_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x01000000)
+#define IXP425_EXP_BUS_CS2_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x02000000)
+#define IXP425_EXP_BUS_CS3_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x03000000)
+#define IXP425_EXP_BUS_CS4_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x04000000)
+#define IXP425_EXP_BUS_CS5_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x05000000)
+#define IXP425_EXP_BUS_CS6_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x06000000)
+#define IXP425_EXP_BUS_CS7_BASE_VIRT	(IXP425_EXP_BUS_BASE2_VIRT + 0x07000000)
+
+#define IXP425_EXP_CS0_OFFSET	0x00
+#define IXP425_EXP_CS1_OFFSET   0x04
+#define IXP425_EXP_CS2_OFFSET   0x08
+#define IXP425_EXP_CS3_OFFSET   0x0C
+#define IXP425_EXP_CS4_OFFSET   0x10
+#define IXP425_EXP_CS5_OFFSET   0x14
+#define IXP425_EXP_CS6_OFFSET   0x18
+#define IXP425_EXP_CS7_OFFSET   0x1C
+#define IXP425_EXP_CFG0_OFFSET	0x20
+#define IXP425_EXP_CFG1_OFFSET	0x24
+#define IXP425_EXP_CFG2_OFFSET	0x28
+#define IXP425_EXP_CFG3_OFFSET	0x2C
+
+/*
+ * Expansion Bus Controller registers.
+ */
+#define IXP425_EXP_REG(x) __REG(IXP425_EXP_CFG_BASE_PHYS+(x))
+
+#define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
+#define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
+#define IXP425_EXP_CS2      IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
+#define IXP425_EXP_CS3      IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
+#define IXP425_EXP_CS4      IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
+#define IXP425_EXP_CS5      IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
+#define IXP425_EXP_CS6      IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
+#define IXP425_EXP_CS7      IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
+
+#define IXP425_EXP_CFG0     IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
+#define IXP425_EXP_CFG1     IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
+#define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
+#define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
+
+#define IXP425_EXP_CS_BYTE_EN     (1 <<  0)
+#define IXP425_EXP_CS_WR_EN       (1 <<  1)
+#define IXP425_EXP_CS_WORD_EN     (1 <<  2)
+#define IXP425_EXP_CS_SPLT_EN     (1 <<  3)
+#define IXP425_EXP_CS_MUX_EN      (1 <<  4)
+#define IXP425_EXP_CS_HRDY_POL    (1 <<  5)
+#define IXP425_EXP_CS_BYTE_RD16   (1 <<  6)
+#define IXP425_EXP_CS_EXP_CHIP    (1 <<  7)
+#define IXP425_EXP_CS_SYNC_INTEL  (1 <<  8)
+#define IXP425_EXP_CS_CNFG(exp)   ((((exp - 9) & 0xF) << 10) | ((1 << (exp - 16)) & 1))
+#define IXP425_EXP_CS_CYC_TYPE(x) (((x) & 0x3) << 14)
+#define IXP425_EXP_CS_T5(x)       (((x) & 0xF) << 16)
+#define IXP425_EXP_CS_T4(x)       (((x) & 0x3) << 20)
+#define IXP425_EXP_CS_T3(x)       (((x) & 0xF) << 22)
+#define IXP425_EXP_CS_T2(x)       (((x) & 0x3) << 26)
+#define IXP425_EXP_CS_T1(x)       (((x) & 0x3) << 28)
+#define IXP425_EXP_CS_PAR_EN      (1 << 30)
+#define IXP425_EXP_CS_EN          (1 << 31)
+
+#define IXP425_FLASH_WRITABLE IXP425_EXP_CS_WR_EN
+#define IXP425_FLASH_DEFAULT  /* (0xbcd23c40) */ \
+        (IXP425_EXP_CS_EN | IXP425_EXP_CS_CNFG(24) | IXP425_EXP_CS_BYTE_RD16 | \
+         IXP425_EXP_CS_T1(3) | IXP425_EXP_CS_T2(3) | IXP425_EXP_CS_T3(3) | \
+         IXP425_EXP_CS_T4(1) | IXP425_EXP_CS_T5(2))
+#define IXP425_FLASH_WRITE (IXP425_FLASH_DEFAULT | IXP425_FLASH_WRITABLE)
+
+/*
+ * UART registers
+ */
+#define IXP425_UART1	0
+#define IXP425_UART2	0x1000
+
+#define IXP425_UART_RBR_OFFSET	0x00
+#define IXP425_UART_THR_OFFSET	0x00
+#define IXP425_UART_DLL_OFFSET	0x00
+#define IXP425_UART_IER_OFFSET	0x04
+#define IXP425_UART_DLH_OFFSET	0x04
+#define IXP425_UART_IIR_OFFSET	0x08
+#define IXP425_UART_FCR_OFFSET	0x00
+#define IXP425_UART_LCR_OFFSET	0x0c
+#define IXP425_UART_MCR_OFFSET	0x10
+#define IXP425_UART_LSR_OFFSET	0x14
+#define IXP425_UART_MSR_OFFSET	0x18
+#define IXP425_UART_SPR_OFFSET	0x1c
+#define IXP425_UART_ISR_OFFSET	0x20
+
+#define IXP425_UART_CFG_BASE_PHYS	(0xc8000000)
+
+#define RBR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET)
+#define THR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET)
+#define DLL(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET)
+#define IER(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET)
+#define DLH(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET)
+#define IIR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET)
+#define FCR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET)
+#define LCR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET)
+#define MCR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET)
+#define LSR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET)
+#define MSR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET)
+#define SPR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET)
+#define ISR(x)	__REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET)
+
+#define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
+#define IER_UUE		(1 << 6)	/* UART Unit Enable */
+#define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
+#define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
+#define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
+#define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt
+					   Enable */
+#define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt
+					   Enable */
+#define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt
+					   Enable */
+
+#define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
+#define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
+#define IIR_TOD		(1 << 3)	/* Time Out Detected */
+#define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
+#define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
+#define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
+
+#define FCR_ITL2	(1 << 7)	/* Interrupt Trigger Level */
+#define FCR_ITL1	(1 << 6)	/* Interrupt Trigger Level */
+#define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
+#define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
+#define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1	(0)
+#define FCR_ITL_8	(FCR_ITL1)
+#define FCR_ITL_16	(FCR_ITL2)
+#define FCR_ITL_32	(FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB	(1 << 7)	/* Divisor Latch Access Bit */
+#define LCR_SB		(1 << 6)	/* Set Break */
+#define LCR_STKYP	(1 << 5)	/* Sticky Parity */
+#define LCR_EPS		(1 << 4)	/* Even Parity Select */
+#define LCR_PEN		(1 << 3)	/* Parity Enable */
+#define LCR_STB		(1 << 2)	/* Stop Bit */
+#define LCR_WLS1	(1 << 1)	/* Word Length Select */
+#define LCR_WLS0	(1 << 0)	/* Word Length Select */
+
+#define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
+#define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
+#define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
+#define LSR_BI		(1 << 4)	/* Break Interrupt */
+#define LSR_FE		(1 << 3)	/* Framing Error */
+#define LSR_PE		(1 << 2)	/* Parity Error */
+#define LSR_OE		(1 << 1)	/* Overrun Error */
+#define LSR_DR		(1 << 0)	/* Data Ready */
+
+#define MCR_LOOP	(1 << 4)	*/
+#define MCR_OUT2	(1 << 3)	/* force MSR_DCD in loopback mode */
+#define MCR_OUT1	(1 << 2)	/* force MSR_RI in loopback mode */
+#define MCR_RTS		(1 << 1)	/* Request to Send */
+#define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
+
+#define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
+#define MSR_RI		(1 << 6)	/* Ring Indicator */
+#define MSR_DSR		(1 << 5)	/* Data Set Ready */
+#define MSR_CTS		(1 << 4)	/* Clear To Send */
+#define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
+#define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
+#define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
+#define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
+
+#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT
+#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
+
+/*
+ * Peripheral Space Registers
+ */
+#define IXP425_UART1_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP425_UART2_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP425_PMU_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP425_INTC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP425_GPIO_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP425_TIMER_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP425_NPEA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x6000)
+#define IXP425_NPEB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x7000)
+#define IXP425_NPEC_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x8000)
+#define IXP425_EthA_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP425_EthB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP425_USB_BASE_PHYS	(IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
+
+#define IXP425_UART1_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP425_UART2_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP425_PMU_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP425_INTC_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP425_GPIO_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP425_TIMER_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP425_NPEA_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x6000)
+#define IXP425_NPEB_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x7000)
+#define IXP425_NPEC_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x8000)
+#define IXP425_EthA_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP425_EthB_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP425_USB_BASE_VIRT	(IXP425_PERIPHERAL_BASE_VIRT + 0xB000)
+
+
+/*
+ * UART Register Definitions , Offsets only as there are 2 UARTS.
+ *   IXP425_UART1_BASE , IXP425_UART2_BASE.
+ */
+
+#undef  UART_NO_RX_INTERRUPT
+
+#define IXP425_UART_XTAL        14745600
+
+/*
+ * Constants to make it easy to access  Interrupt Controller registers
+ */
+#define IXP425_ICPR_OFFSET	0x00 /* Interrupt Status */
+#define IXP425_ICMR_OFFSET	0x04 /* Interrupt Enable */
+#define IXP425_ICLR_OFFSET	0x08 /* Interrupt IRQ/FIQ Select */
+#define IXP425_ICIP_OFFSET      0x0C /* IRQ Status */
+#define IXP425_ICFP_OFFSET	0x10 /* FIQ Status */
+#define IXP425_ICHR_OFFSET	0x14 /* Interrupt Priority */
+#define IXP425_ICIH_OFFSET	0x18 /* IRQ Highest Pri Int */
+#define IXP425_ICFH_OFFSET	0x1C /* FIQ Highest Pri Int */
+
+/*
+ * Interrupt Controller Register Definitions.
+ */
+#define IXP425_INTC_REG(x) __REG(IXP425_INTC_BASE_PHYS+(x))
+
+#define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
+#define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
+#define IXP425_ICLR     IXP425_INTC_REG(IXP425_ICLR_OFFSET)
+#define IXP425_ICIP     IXP425_INTC_REG(IXP425_ICIP_OFFSET)
+#define IXP425_ICFP     IXP425_INTC_REG(IXP425_ICFP_OFFSET)
+#define IXP425_ICHR     IXP425_INTC_REG(IXP425_ICHR_OFFSET)
+#define IXP425_ICIH     IXP425_INTC_REG(IXP425_ICIH_OFFSET)
+#define IXP425_ICFH     IXP425_INTC_REG(IXP425_ICFH_OFFSET)
+
+/*
+ * Constants to make it easy to access GPIO registers
+ */
+#define IXP425_GPIO_GPOUTR_OFFSET       0x00
+#define IXP425_GPIO_GPOER_OFFSET        0x04
+#define IXP425_GPIO_GPINR_OFFSET        0x08
+#define IXP425_GPIO_GPISR_OFFSET        0x0C
+#define IXP425_GPIO_GPIT1R_OFFSET	0x10
+#define IXP425_GPIO_GPIT2R_OFFSET	0x14
+#define IXP425_GPIO_GPCLKR_OFFSET	0x18
+
+/*
+ * GPIO Register Definitions.
+ * [Only perform 32bit reads/writes]
+ */
+#define IXP425_GPIO_REG(x) __REG(IXP425_GPIO_BASE_PHYS+(x))
+
+#define IXP425_GPIO_GPOUTR	IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
+#define IXP425_GPIO_GPOER       IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
+#define IXP425_GPIO_GPINR       IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET)
+#define IXP425_GPIO_GPISR       IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET)
+#define IXP425_GPIO_GPIT1R      IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET)
+#define IXP425_GPIO_GPIT2R      IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET)
+#define IXP425_GPIO_GPCLKR      IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET)
+
+/*
+ * Macros to make it easy to access the GPIO registers
+ */
+#define GPIO_OUTPUT_ENABLE(line)	*IXP425_GPIO_GPOER &= ~(1 << (line))
+#define GPIO_OUTPUT_DISABLE(line)	*IXP425_GPIO_GPOER |= (1 << (line))
+#define GPIO_OUTPUT_SET(line)		*IXP425_GPIO_GPOUTR |= (1 << (line))
+#define GPIO_OUTPUT_CLEAR(line)		*IXP425_GPIO_GPOUTR &= ~(1 << (line))
+#define GPIO_INT_TYPE_ACTIVE_LOW   0
+#define GPIO_INT_TYPE_ACTIVE_HIGH  1
+#define GPIO_INT_TYPE_RISING_EDGE  2
+#define GPIO_INT_TYPE_FALLING_EDGE 3
+#define GPIO_INT_TYPE_TRANSITIONAL 4
+
+#ifndef __ASSEMBLY__
+static inline void GPIO_INT_SET(unsigned int line, unsigned int type) {
+	u32 val;
+
+	if (type > 4)
+		return;
+
+	if (line <= 7) {
+		val = *IXP425_GPIO_GPIT1R;
+		val &= ~(0x7 << (line * 3));
+		val |= (type << (line * 3));
+		*IXP425_GPIO_GPIT1R = val;
+	} else if (line <= 12) {
+		line &= 0x7;
+		val = *IXP425_GPIO_GPIT2R;
+		val &= ~(0x7 << (line * 3));
+		val |= (type << (line * 3));
+		*IXP425_GPIO_GPIT2R = val;
+	}
+}
+#define GPIO_INT_ACT_LOW_SET(line) GPIO_INT_SET((line), GPIO_INT_TYPE_ACTIVE_LOW)
+#endif
+
+/*
+ * Constants to make it easy to access Timer Control/Status registers
+ */
+#define IXP425_OSTS_OFFSET	0x00  /* Continious TimeStamp */
+#define IXP425_OST1_OFFSET	0x04  /* Timer 1 Timestamp */
+#define IXP425_OSRT1_OFFSET	0x08  /* Timer 1 Reload */
+#define IXP425_OST2_OFFSET	0x0C  /* Timer 2 Timestamp */
+#define IXP425_OSRT2_OFFSET	0x10  /* Timer 2 Reload */
+#define IXP425_OSWT_OFFSET	0x14  /* Watchdog Timer */
+#define IXP425_OSWE_OFFSET	0x18  /* Watchdog Enable */
+#define IXP425_OSWK_OFFSET	0x1C  /* Watchdog Key */
+#define IXP425_OSST_OFFSET	0x20  /* Timer Status */
+
+/*
+ * Operating System Timer Register Definitions.
+ */
+
+#define IXP425_TIMER_REG(x) __REG(IXP425_TIMER_BASE_PHYS+(x))
+
+#if 0 /* test-only: also defined in npe/include/... */
+#define IXP425_OSTS	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
+#endif
+#define IXP425_OST1	IXP425_TIMER_REG(IXP425_OST1_OFFSET)
+#define IXP425_OSRT1	IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
+#define IXP425_OST2	IXP425_TIMER_REG(IXP425_OST2_OFFSET)
+#define IXP425_OSRT2	IXP425_TIMER_REG(IXP425_OSRT2_OFFSET)
+#define IXP425_OSWT	IXP425_TIMER_REG(IXP425_OSWT_OFFSET)
+#define IXP425_OSWE	IXP425_TIMER_REG(IXP425_OSWE_OFFSET)
+#define IXP425_OSWK	IXP425_TIMER_REG(IXP425_OSWK_OFFSET)
+#define IXP425_OSST	IXP425_TIMER_REG(IXP425_OSST_OFFSET)
+
+/*
+ * Timer register values and bit definitions
+ */
+#define IXP425_OST_ENABLE              BIT(0)
+#define IXP425_OST_ONE_SHOT            BIT(1)
+/* Low order bits of reload value ignored */
+#define IXP425_OST_RELOAD_MASK         (0x3)
+#define IXP425_OST_DISABLED            (0x0)
+#define IXP425_OSST_TIMER_1_PEND       BIT(0)
+#define IXP425_OSST_TIMER_2_PEND       BIT(1)
+#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
+#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
+#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)
+
+/*
+ * Constants to make it easy to access PCI Control/Status registers
+ */
+#define PCI_NP_AD_OFFSET		0x00
+#define PCI_NP_CBE_OFFSET		0x04
+#define PCI_NP_WDATA_OFFSET		0x08
+#define PCI_NP_RDATA_OFFSET		0x0c
+#define PCI_CRP_AD_CBE_OFFSET		0x10
+#define PCI_CRP_WDATA_OFFSET		0x14
+#define PCI_CRP_RDATA_OFFSET		0x18
+#define PCI_CSR_OFFSET			0x1c
+#define PCI_ISR_OFFSET			0x20
+#define PCI_INTEN_OFFSET		0x24
+#define PCI_DMACTRL_OFFSET		0x28
+#define PCI_AHBMEMBASE_OFFSET		0x2c
+#define PCI_AHBIOBASE_OFFSET		0x30
+#define PCI_PCIMEMBASE_OFFSET		0x34
+#define PCI_AHBDOORBELL_OFFSET		0x38
+#define PCI_PCIDOORBELL_OFFSET		0x3C
+#define PCI_ATPDMA0_AHBADDR_OFFSET	0x40
+#define PCI_ATPDMA0_PCIADDR_OFFSET	0x44
+#define PCI_ATPDMA0_LENADDR_OFFSET	0x48
+#define PCI_ATPDMA1_AHBADDR_OFFSET	0x4C
+#define PCI_ATPDMA1_PCIADDR_OFFSET	0x50
+#define PCI_ATPDMA1_LENADDR_OFFSET	0x54
+
+/*
+ * PCI Control/Status Registers
+ */
+#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x)))
+
+#define PCI_NP_AD               IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
+#define PCI_NP_CBE              IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)
+#define PCI_NP_WDATA            IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET)
+#define PCI_NP_RDATA            IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET)
+#define PCI_CRP_AD_CBE          IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
+#define PCI_CRP_WDATA           IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
+#define PCI_CRP_RDATA           IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
+#define PCI_CSR                 IXP425_PCI_CSR(PCI_CSR_OFFSET)
+#define PCI_ISR                 IXP425_PCI_CSR(PCI_ISR_OFFSET)
+#define PCI_INTEN               IXP425_PCI_CSR(PCI_INTEN_OFFSET)
+#define PCI_DMACTRL             IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
+#define PCI_AHBMEMBASE          IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
+#define PCI_AHBIOBASE           IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET)
+#define PCI_PCIMEMBASE          IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
+#define PCI_AHBDOORBELL         IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
+#define PCI_PCIDOORBELL         IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
+#define PCI_ATPDMA0_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
+#define PCI_ATPDMA0_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
+#define PCI_ATPDMA0_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
+#define PCI_ATPDMA1_AHBADDR     IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
+#define PCI_ATPDMA1_PCIADDR     IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
+#define PCI_ATPDMA1_LENADDR     IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
+
+/*
+ * PCI register values and bit definitions
+ */
+
+/* CSR bit definitions */
+#define PCI_CSR_HOST    	BIT(0)
+#define PCI_CSR_ARBEN   	BIT(1)
+#define PCI_CSR_ADS     	BIT(2)
+#define PCI_CSR_PDS     	BIT(3)
+#define PCI_CSR_ABE     	BIT(4)
+#define PCI_CSR_DBT     	BIT(5)
+#define PCI_CSR_ASE     	BIT(8)
+#define PCI_CSR_IC      	BIT(15)
+
+/* ISR (Interrupt status) Register bit definitions */
+#define PCI_ISR_PSE     	BIT(0)
+#define PCI_ISR_PFE     	BIT(1)
+#define PCI_ISR_PPE     	BIT(2)
+#define PCI_ISR_AHBE    	BIT(3)
+#define PCI_ISR_APDC    	BIT(4)
+#define PCI_ISR_PADC    	BIT(5)
+#define PCI_ISR_ADB     	BIT(6)
+#define PCI_ISR_PDB     	BIT(7)
+
+/* INTEN (Interrupt Enable) Register bit definitions */
+#define PCI_INTEN_PSE   	BIT(0)
+#define PCI_INTEN_PFE   	BIT(1)
+#define PCI_INTEN_PPE   	BIT(2)
+#define PCI_INTEN_AHBE  	BIT(3)
+#define PCI_INTEN_APDC  	BIT(4)
+#define PCI_INTEN_PADC  	BIT(5)
+#define PCI_INTEN_ADB   	BIT(6)
+#define PCI_INTEN_PDB   	BIT(7)
+
+/*
+ * Shift value for byte enable on NP cmd/byte enable register
+ */
+#define IXP425_PCI_NP_CBE_BESL		4
+
+/*
+ * PCI commands supported by NP access unit
+ */
+#define NP_CMD_IOREAD			0x2
+#define NP_CMD_IOWRITE			0x3
+#define NP_CMD_CONFIGREAD		0xa
+#define NP_CMD_CONFIGWRITE		0xb
+#define NP_CMD_MEMREAD			0x6
+#define	NP_CMD_MEMWRITE			0x7
+
+#if 0
+#ifndef __ASSEMBLY__
+extern int ixp425_pci_read(u32 addr, u32 cmd, u32 *data);
+extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data);
+extern void ixp425_pci_init(void *);
+#endif
+#endif
+
+/*
+ * Constants for CRP access into local config space
+ */
+#define CRP_AD_CBE_BESL         20
+#define CRP_AD_CBE_WRITE        BIT(16)
+
+/*
+ * Clock Speed Definitions.
+ */
+#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS   */
+
+
+#endif
+
