IXP42x cpu support fixes

This cleans up the IXP425 header file to something a bit more sane.

Signed-off-by: Hendrik Sattler

---
 cpu/ixp/interrupts.c              |    3 -
 cpu/ixp/serial.c                  |   28 ++++++------
 include/asm-arm/arch-ixp/ixp425.h |   82 ++++++++++++++++++++++++++------------
 3 files changed, 72 insertions(+), 41 deletions(-)

--- u-boot-1.3.4.orig/cpu/ixp/interrupts.c
+++ u-boot-1.3.4/cpu/ixp/interrupts.c
@@ -85,9 +85,6 @@
 	timestamp = 0;
 }
 
-#endif /* #ifdef CONFIG_USE_IRQ */
-
-#ifdef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
 	int irq = next_irq();
--- u-boot-1.3.4.orig/cpu/ixp/serial.c
+++ u-boot-1.3.4/cpu/ixp/serial.c
@@ -50,20 +50,20 @@
 	else
 		hang ();
 
-	IER(uart) = 0;					/* Disable for now */
-	FCR(uart) = 0;					/* No fifos enabled */
+	*IER(uart) = 0;					/* Disable for now */
+	*FCR(uart) = 0;					/* No fifos enabled */
 
 	/* set baud rate */
-	LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
-	DLL(uart) = quot & 0xff;
-	DLH(uart) = quot >> 8;
-	LCR(uart) = LCR_WLS0 | LCR_WLS1;
+	*LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
+	*DLL(uart) = quot & 0xff;
+	*DLH(uart) = quot >> 8;
+	*LCR(uart) = LCR_WLS0 | LCR_WLS1;
 #ifdef CONFIG_SERIAL_RTS_ACTIVE
-	MCR(uart) = MCR_RTS;				/* set RTS active */
+	*MCR(uart) = MCR_RTS;				/* set RTS active */
 #else
-	MCR(uart) = 0;					/* set RTS inactive */
+	*MCR(uart) = 0;					/* set RTS inactive */
 #endif
-	IER(uart) = IER_UUE;
+	*IER(uart) = IER_UUE;
 }
 
 /*
@@ -85,9 +85,9 @@
 void serial_putc (const char c)
 {
 	/* wait for room in the tx FIFO on UART */
-	while ((LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0);
+	while ((*LSR(CFG_IXP425_CONSOLE) & LSR_TEMT) == 0);
 
-	THR(CFG_IXP425_CONSOLE) = c;
+	*THR(CFG_IXP425_CONSOLE) = c;
 
 	/* If \n, also do \r */
 	if (c == '\n')
@@ -101,7 +101,7 @@
  */
 int serial_tstc (void)
 {
-	return LSR(CFG_IXP425_CONSOLE) & LSR_DR;
+	return *LSR(CFG_IXP425_CONSOLE) & LSR_DR;
 }
 
 /*
@@ -111,9 +111,9 @@
  */
 int serial_getc (void)
 {
-	while (!(LSR(CFG_IXP425_CONSOLE) & LSR_DR));
+	while (!(*LSR(CFG_IXP425_CONSOLE) & LSR_DR));
 
-	return (char) RBR(CFG_IXP425_CONSOLE) & 0xff;
+	return (char) *RBR(CFG_IXP425_CONSOLE) & 0xff;
 }
 
 void
--- u-boot-1.3.4.orig/include/asm-arm/arch-ixp/ixp425.h
+++ u-boot-1.3.4/include/asm-arm/arch-ixp/ixp425.h
@@ -23,8 +23,7 @@
 # undef __REG
 # ifndef __ASSEMBLY__
 #  define io_p2v(PhAdd)    (PhAdd)
-#  define __REG(x)	(*((volatile u32 *)io_p2v(x)))
-#  define __REG2(x,y)	(*(volatile u32 *)((u32)&__REG(x) + (y)))
+#  define __REG(x)	((volatile u32 *)io_p2v(x))
 # else
 #  define __REG(x) (x)
 # endif
@@ -124,10 +123,6 @@
 #define IXP425_EXP_BUS_CS6_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
 #define IXP425_EXP_BUS_CS7_BASE_PHYS	(IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
 
-#define IXP425_FLASH_WRITABLE	(0x2)
-#define IXP425_FLASH_DEFAULT	(0xbcd23c40)
-#define IXP425_FLASH_WRITE	(0xbcd23c42)
-
 #define IXP425_EXP_CS0_OFFSET	0x00
 #define IXP425_EXP_CS1_OFFSET   0x04
 #define IXP425_EXP_CS2_OFFSET   0x08
@@ -144,11 +139,7 @@
 /*
  * Expansion Bus Controller registers.
  */
-#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
-#else
-#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
-#endif
+#define IXP425_EXP_REG(x) __REG(IXP425_EXP_CFG_BASE_PHYS+(x))
 
 #define IXP425_EXP_CS0      IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
 #define IXP425_EXP_CS1      IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
@@ -164,6 +155,32 @@
 #define IXP425_EXP_CFG2     IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
 #define IXP425_EXP_CFG3     IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
 
+#define IXP425_EXP_CS_BYTE_EN     (1 <<  0)
+#define IXP425_EXP_CS_WR_EN       (1 <<  1)
+#define IXP425_EXP_CS_WORD_EN     (1 <<  2)
+#define IXP425_EXP_CS_SPLT_EN     (1 <<  3)
+#define IXP425_EXP_CS_MUX_EN      (1 <<  4)
+#define IXP425_EXP_CS_HRDY_POL    (1 <<  5)
+#define IXP425_EXP_CS_BYTE_RD16   (1 <<  6)
+#define IXP425_EXP_CS_EXP_CHIP    (1 <<  7)
+#define IXP425_EXP_CS_SYNC_INTEL  (1 <<  8)
+#define IXP425_EXP_CS_CNFG(exp)   (((exp - 9) & 0xF) << 10)
+#define IXP425_EXP_CS_CYC_TYPE(x) (((x) & 0x3) << 14)
+#define IXP425_EXP_CS_T5(x)       (((x) & 0xF) << 16)
+#define IXP425_EXP_CS_T4(x)       (((x) & 0x3) << 20)
+#define IXP425_EXP_CS_T3(x)       (((x) & 0xF) << 22)
+#define IXP425_EXP_CS_T2(x)       (((x) & 0x3) << 26)
+#define IXP425_EXP_CS_T1(x)       (((x) & 0x3) << 28)
+#define IXP425_EXP_CS_PAR_EN      (1 << 30)
+#define IXP425_EXP_CS_EN          (1 << 31)
+
+#define IXP425_FLASH_WRITABLE IXP425_EXP_CS_WR_EN
+#define IXP425_FLASH_DEFAULT  /* (0xbcd23c40) */ \
+        (IXP425_EXP_CS_EN | IXP425_EXP_CS_CNFG(24) | IXP425_EXP_CS_BYTE_RD16 | \
+         IXP425_EXP_CS_T1(3) | IXP425_EXP_CS_T2(3) | IXP425_EXP_CS_T3(3) | \
+         IXP425_EXP_CS_T4(1) | IXP425_EXP_CS_T5(2))
+#define IXP425_FLASH_WRITE (IXP425_FLASH_DEFAULT | IXP425_FLASH_WRITABLE)
+
 /*
  * SDRAM Controller registers.
  */
@@ -316,11 +333,7 @@
 /*
  * Interrupt Controller Register Definitions.
  */
-#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
-#else
-#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
-#endif
+#define IXP425_INTC_REG(x) __REG(IXP425_INTC_BASE_PHYS+(x))
 
 #define IXP425_ICPR     IXP425_INTC_REG(IXP425_ICPR_OFFSET)
 #define IXP425_ICMR     IXP425_INTC_REG(IXP425_ICMR_OFFSET)
@@ -365,8 +378,34 @@
 #define GPIO_OUTPUT_DISABLE(line)	*IXP425_GPIO_GPOER |= (1 << (line))
 #define GPIO_OUTPUT_SET(line)		*IXP425_GPIO_GPOUTR |= (1 << (line))
 #define GPIO_OUTPUT_CLEAR(line)		*IXP425_GPIO_GPOUTR &= ~(1 << (line))
-#define GPIO_INT_ACT_LOW_SET(line)	*IXP425_GPIO_GPIT1R = \
-		(*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3))
+#define GPIO_INT_TYPE_ACTIVE_LOW   0
+#define GPIO_INT_TYPE_ACTIVE_HIGH  1
+#define GPIO_INT_TYPE_RISING_EDGE  2
+#define GPIO_INT_TYPE_FALLING_EDGE 3
+#define GPIO_INT_TYPE_TRANSITIONAL 4
+
+#ifndef __ASSEMBLY__
+static inline void GPIO_INT_SET(unsigned int line, unsigned int type) {
+	u32 val;
+
+	if (type > 4)
+		return;
+
+	if (line <= 7) {
+		val = *IXP425_GPIO_GPIT1R;
+		val &= ~(0x7 << (line * 3));
+		val |= (type << (line * 3));
+		*IXP425_GPIO_GPIT1R = val;
+	} else if (line <= 12) {
+		line &= 0x7;
+		val = *IXP425_GPIO_GPIT2R;
+		val &= ~(0x7 << (line * 3));
+		val |= (type << (line * 3));
+		*IXP425_GPIO_GPIT2R = val;
+	}
+}
+#define GPIO_INT_ACT_LOW_SET(line) GPIO_INT_SET((line), GPIO_INT_TYPE_ACTIVE_LOW)
+#endif
 
 /*
  * Constants to make it easy to access Timer Control/Status registers
@@ -384,12 +423,7 @@
 /*
  * Operating System Timer Register Definitions.
  */
-
-#ifndef __ASSEMBLY__
-#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x)))
-#else
-#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
-#endif
+#define IXP425_TIMER_REG(x) __REG(IXP425_TIMER_BASE_PHYS+(x))
 
 #if 0 /* test-only: also defined in npe/include/... */
 #define IXP425_OSTS	IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
