This adds the support for the Adi Sidewinder Reference Board.
It depends on the IXP465 support in U-Boot.

Signed-off-by: Hendrik Sattler

---
 Makefile                      |    3 
 board/sidewinder/Makefile     |   46 ++++++++++
 board/sidewinder/config.mk    |    3 
 board/sidewinder/sidewinder.c |  153 +++++++++++++++++++++++++++++++++++
 board/sidewinder/u-boot.lds   |   57 +++++++++++++
 include/configs/sidewinder.h  |  179 ++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 441 insertions(+)

--- u-boot-1.3.4.orig/Makefile
+++ u-boot-1.3.4/Makefile
@@ -2594,6 +2594,9 @@
 actux4_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm ixp actux4
 
+sidewinder_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm ixp sidewinder
+
 cerf250_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm pxa cerf250
 
--- /dev/null
+++ u-boot-1.3.4/board/sidewinder/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2008
+# Michael Trimarchi, Evidence S.r.l
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= sidewinder.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+++ u-boot-1.3.4/board/sidewinder/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE = 0x07600000
+# include NPE ethernet driver
+BOARDLIBS = $(obj)cpu/ixp/npe/libnpe.a
--- /dev/null
+++ u-boot-1.3.4/board/sidewinder/sidewinder.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2008
+ * Michael Trimarchi, Evidence S.r.l, [EMAIL PROTECTED]
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/ixp465.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/* arch number of IXDP */
+	gd->bd->bi_arch_number = MACH_TYPE_SIDEWINDER;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	/* tell common/main.c that history can work */
+	gd->flags |= GD_FLG_RELOC;
+
+	/* PCI INTC (USB2.0) */
+	GPIO_OUTPUT_DISABLE(9);
+	GPIO_INT_SET(9, GPIO_INT_TYPE_ACTIVE_LOW);
+
+	/* PCI INTB */
+	GPIO_OUTPUT_DISABLE(10);
+	GPIO_INT_SET(10, GPIO_INT_TYPE_ACTIVE_LOW);
+
+	/* PCI INTA */
+	GPIO_OUTPUT_DISABLE(11);
+	GPIO_INT_SET(11, GPIO_INT_TYPE_ACTIVE_LOW);
+
+	/* GPIO14 is 33MHz PCI clock
+	 * GPIO15 is 33Mhz expansion bus clock
+	 */
+	*IXP425_GPIO_GPCLKR = 0x01FF01FF;
+	GPIO_OUTPUT_ENABLE(14);
+	GPIO_OUTPUT_ENABLE(15);
+
+	/* The upper part of the flash is at
+	 * chipselect 1 but the start code only
+	 * sets chipselect 0
+	 */
+	*IXP425_EXP_CS1 = *IXP425_EXP_CS0;
+	*IXP425_EXP_CS4 = 0xbfff0002;
+	*IXP425_EXP_CS6 = 0xbfff0002;
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard(void)
+{
+	char *s = getenv("serial#");
+
+	puts("Board: ADI Sidewinder Reference Platform");
+
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	return (0);
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
+
+	return 0;
+}
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+extern struct pci_controller hose;
+extern void pci_ixp_init(struct pci_controller * hose);
+
+void pci_init_board(void)
+{
+	extern void pci_ixp_init (struct pci_controller *hose);
+
+	pci_ixp_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy (void)
+{
+	char* dev[] = {
+		"NPE0",
+#if defined(CONFIG_HAS_ETH1)
+		"NPE1",
+#endif
+	};
+	unsigned char addr[] = {
+		CONFIG_PHY_ADDR,
+#if defined(CONFIG_HAS_ETH1)
+		CONFIG_PHY1_ADDR,
+#endif
+	};
+	int i = 0;
+
+	for (; i < sizeof(dev)/sizeof(*dev); ++i) {
+		unsigned short bmcr, anar;
+
+		/* initialize the PHY */
+		(void)miiphy_reset (dev[i], addr[i]);
+
+		/* software power-down during configuration,
+		 * enable auto-negotiation 10/100 HD/FD
+		 */
+		if (miiphy_read(dev[i], addr[i], PHY_BMCR, &bmcr))
+			continue;
+		bmcr |= PHY_BMCR_AUTON | PHY_BMCR_100MB | PHY_BMCR_DPLX | PHY_BMCR_POWD;
+		if (miiphy_write(dev[i], addr[i], PHY_BMCR, bmcr))
+			continue;
+		/* enable 100FD, 100TX, 10FD, 10T */
+		if (miiphy_read(dev[i], addr[i], PHY_ANAR, &anar))
+			continue;
+		if (miiphy_write(dev[i], addr[i], PHY_ANAR, anar | 0x01e0))
+			continue;
+		/* set to normal operation and restart auto-negotiation */
+		bmcr &= ~(PHY_BMCR_POWD | PHY_BMCR_ISO | PHY_BMCR_LOOP);
+		bmcr |= PHY_BMCR_RST_NEG;
+		miiphy_write(dev[i], addr[i], PHY_BMCR, bmcr);
+	}
+}
+#endif
--- /dev/null
+++ u-boot-1.3.4/board/sidewinder/u-boot.lds
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/ixp/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss (NOLOAD) : { *(.bss) }
+	_end = .;
+}
+
--- /dev/null
+++ u-boot-1.3.4/include/configs/sidewinder.h
@@ -0,0 +1,179 @@
+/*
+ * ADI Sidewinder Demo-Board
+ * Copyright (C) 2008 Hendrik sattler <hendrik.sattler@mixed-mode.de>
+ */
+
+/* flash layout:
+ * start    | end      | size  | name         | linux
+ * ---------+----------+-------+--------------+------
+ * 50000000 | 5003FFFF | 256K  | u-boot       | mtd0
+ * 50040000 | 5005FFFF | 128K  | env          | mtd1
+ * 50060000 | 5007FFFF | 128K  | npe_firmware | mtd2
+ * 50080000 | ........ | ....  | kernel       | mtd3
+ * ...
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_IXP465 1
+#define CONFIG_ADI_SIDEWINDER 1
+
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+#undef CONFIG_USE_IRQ
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BOOTDELAY 0
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#undef CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+               "mtdids=nand0=IXP4XX-Flash.0\0" \
+               "mtdparts=mtdparts=IXP4XX-Flash.0:256k(u-boot),128k(env)ro,128k(npe_firmware),1536k(kernel),-(system)\0" \
+               "partition=nand0,4\0" \
+               "bootargs_setup=setenv bootargs root=/dev/mtdblock4 rootfstype=jffs2 console=ttyS0,$(baudrate) $(mtdparts) ecc=on rw\0"
+
+#define CONFIG_BOOTCOMMAND "run bootargs_setup; bootm"
+#undef CONFIG_BOOTARGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+#undef CONFIG_IXP425_COMPAT
+
+#undef CFG_CLKS_IN_HZ
+
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+
+/* ethernet network configuration */
+#define CONFIG_IXP4XX_NPE 1
+#define CONFIG_PHY_ADDR   5
+#define CONFIG_NET_MULTI  1 /* net/eth.c needs this */
+#define CONFIG_RESET_PHY_R 1
+
+/* console configuration */
+#define CFG_IXP425_CONSOLE IXP425_UART1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CMDLINE_EDITING
+
+#define CFG_LONGHELP
+#define CFG_PROMPT              "sw> "
+#define CFG_CBSIZE              1024
+#define CFG_PBSIZE              (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_MAXARGS             32
+#define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
+#define CFG_MEMTEST_START       0x00800000      /* memtest works on     */
+#define CFG_MEMTEST_END         0x015fffff      /* 4 ... 8 MB in DRAM   */
+
+#define CFG_HZ                  66666666
+
+/*the stack sizes are set up in start.S using the settings below */
+#define CONFIG_STACKSIZE        (128*1024)
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS    2
+#define PHYS_SDRAM_1            0x00000000
+#define PHYS_SDRAM_1_SIZE       0x04000000
+#define PHYS_SDRAM_2            (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
+#define PHYS_SDRAM_2_SIZE       0x04000000
+#define PHYS_SDRAM_END		(PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)
+
+#define CFG_SDRAM_BASE          PHYS_SDRAM_1
+#define CFG_SDRAM_SIZE          PHYS_SDRAM_END
+#define CONFIG_SDRAM_ECC
+
+#define PHYS_FLASH_1            0x50000000
+#define PHYS_FLASH_2            0x52000000
+#define PHYS_FLASH_SIZE         0x04000000
+#define PHYS_FLASH_BANK_SIZE    0x02000000
+#define PHYS_FLASH_SECT_SIZE    0x00020000
+
+#define CFG_FLASH_BASE          PHYS_FLASH_1
+
+#define CFG_MONITOR_BASE        CFG_FLASH_BASE
+#define CFG_MONITOR_LEN         (2 * PHYS_FLASH_SECT_SIZE)
+
+/* Flash (CS0) setting */
+#define IXP425_EXP_CS0_INIT 1
+#define CFG_EXP_CS0             0x95110242
+
+/* FLASH and environment organization */
+#define CFG_MAX_FLASH_BANKS     (PHYS_FLASH_SIZE / PHYS_FLASH_BANK_SIZE)
+#define CFG_MAX_FLASH_SECT      (PHYS_FLASH_SIZE / PHYS_FLASH_SECT_SIZE)
+#define CFG_FLASH_CFI		1
+#define CFG_FLASH_CFI_DRIVER	1
+#define	CFG_ENV_IS_IN_FLASH	1
+#define CFG_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CFG_FLASH_BANKS_LIST    { PHYS_FLASH_1, PHYS_FLASH_2 }
+#define CONFIG_FLASH_SHOW_PROGRESS 45
+
+#define CFG_FLASH_PROTECTION    1
+#define CFG_FLASH_ERASE_TOUT    120000
+#define CFG_FLASH_WRITE_TOUT    5000
+
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_USE_BUFFER_WRITE
+
+#define CFG_ENV_SECT_SIZE       PHYS_FLASH_SECT_SIZE
+#define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define	CFG_ENV_SIZE		CFG_ENV_SECT_SIZE
+
+/* size of malloc() pool */
+#define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+
+#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE (CFG_ENV_ADDR + CFG_ENV_SIZE)
+
+/* the default address for commands like iminfo and bootm
+ * make it point to default kernel location
+ */
+#define CFG_LOAD_ADDR           (CONFIG_IXP4XX_NPE_EXT_UCODE_BASE + PHYS_FLASH_SECT_SIZE) /* default load address */
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE      32
+
+/* ADI Sidewinder:
+   tRCD=15ns,
+   tRP=15ns,
+   tRAS=40ns,
+   CAS=2,
+   WTR=2,
+   tRC=55ns,
+   tRFC=70ns,
+   tWR=15ns
+
+   BANK0 = 256Mx16 (64MB)
+   BANK1 = 256Mx16 (64MB)
+ */
+/*
+ * DDR-SDRAM configuration
+ */
+#define CFG_DDR_SDCR0_INIT (0x62220006)
+#define CFG_DDR_SDCR1_INIT (0x24509074)
+#define CFG_DDR_SBR0_INIT  (DDR_SBR_256Mx16 | DDR_SBR(PHYS_SDRAM_2))
+#define CFG_DDR_SBR1_INIT  (DDR_SBR_256Mx16 | DDR_SBR(PHYS_SDRAM_END))
+#define CFG_SDRAM_REFRESH_CNT (0x00000410)
+
+#endif /* __CONFIG_H */
