HI Stephen,
On Wed, Feb 27, 2013 at 4:36 PM, Stephen Warren swarren@wwwdotorg.org wrote:
On 02/27/2013 05:30 PM, Simon Glass wrote:
On Tue, Feb 26, 2013 at 2:28 PM, Stephen Warren swarren@wwwdotorg.org wrote:
From: Stephen Warren swarren@nvidia.com
Various errata exist in the Cortex-A9 CPU, and may be worked around by setting some bits in a CP15 diagnostic register. Add code to implement the workarounds, enabled by new CONFIG_ options.
This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S, and modified to remove the logic to conditionally apply the WAR (since we know exactly which CPU we're running on given the U-Boot configuration), and use r0 instead of r10 for consistency with the rest of U-Boot's cpu_init_cp15().
Signed-off-by: Stephen Warren swarren@nvidia.com
Acked-by: Simon Glass sjg@chromium.org
Good to have. Although I wonder why we wouldn't want to probe it in U-Boot as with Linux?
I figured it wasn't worth the complexity initially. Right now, U-Boot is built for a specific board (or just perhaps a small set of almost identical boards), so we know exactly which CPU rev is present. If this becomes false (e.g. DT works so well we can do a combined Tegra20+Tegra30 U-Boot), we can always add the conditional logic in when we need it.
Fair enough, thank you.
Regards, Simon