On 10/5/22 12:38, Andre Przywara wrote:
While playing around with QEMU's semihosting implementation, I stared at our semihosting trap code, and found some issues, that this mini-series fixes.
Please have a look!
Cheers, Andre
Andre Przywara (3): arm: smh: specify Thumb trap instruction arm: smh: Make semihosting trap calls more robust arm: smh: Allow semihosting trap calls to be inlined
arch/arm/lib/semihosting.c | 44 +++++++++++++++++++++++++++----------- 1 file changed, 31 insertions(+), 13 deletions(-)
This all LGTM
Although I wonder if we should just move smh_trap into an assembly file. I think that would apply most of these optimization barriers.
Your series will also confict with Kautuk's series [1]. I think the bugs you described above will apply to RISC-V as well.
--Sean
[1] https://lore.kernel.org/all/20220923070320.617623-1-kconsul@ventanamicro.com...