Re: [U-Boot] [PATCH V2 2/3] pci: tegra: port to standard clock/reset/pwr domain APIs

6 Aug 2016


      On 5 August 2016 at 16:10, Stephen Warren swarren@wwwdotorg.org wrote:
...
From: Stephen Warren swarren@nvidia.com
Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.
On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.
Signed-off-by: Stephen Warren swarren@nvidia.com
v2: Add TODO comment describing the messy ifdefs.
drivers/pci/Kconfig     |   1 +
 drivers/pci/pci_tegra.c | 163 ++++++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 159 insertions(+), 5 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org