-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Wednesday, March 24, 2021 1:25 PM To: Tan, Ley Foon ley.foon.tan@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Hi Ley Foon,
-----Original Message----- From: Tan, Ley Foon ley.foon.tan@intel.com Sent: Tuesday, March 23, 2021 6:34 PM To: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com; u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com Subject: RE: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Monday, March 15, 2021 10:37 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org;
Gan,
Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 1/2] arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com
arch/arm/mach-socfpga/clock_manager.c | 15 ++++++++++++--
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 ------ arch/arm/mach-socfpga/clock_manager_s10.c | 6 ------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 - 5 files changed, 16 insertions(+), 16 deletions(-)
[...]
unsigned int cm_get_spi_controller_clk_hz(void) { u32 clock = cm_get_l3_main_clk_hz(); diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 1f734bcd65..0f0cb230fa 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -12,6 +12,10 @@ phys_addr_t socfpga_get_clkmgr_addr(void); void cm_wait_for_lock(u32 mask); int cm_wait_for_fsm(void); void cm_print_clock_quick_summary(void);
+#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +unsigned int cm_get_qspi_controller_clk_hz(void); +#endif #endif
If this is for soc64, move to _SOC64.h file?
We do have clock_manager_soc64.h which shared by both stratix 10 and agilex.
clock_manager_s10.h if specific for CONFIG_TARGET_SOCFPGA_STRATIX10. clock_manager_s10.h includes clock_manager_soc64.h and it contains additional struct and macro for s10.
cm_get_qspi_controller_clk_hz() is for cyclone 5 and Arria 10 too, can just function prototype in clock_manager.h and use for all devices.
Ley Foon