Hi Jagan,
On Mon, Feb 15, 2016 at 4:49 AM, Jagan Teki jteki@openedev.com wrote:
mp2580 will take care of tx and rx mode's so there is no need to differentiate these into spi layer level hence replaced all mode_rx macros with mode.
Cc: Simon Glass sjg@chromium.org Cc: Bin Meng bmeng.cn@gmail.com Cc: Mugunthan V N mugunthanvnm@ti.com Cc: Michal Simek michal.simek@xilinx.com Cc: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Jagan Teki jteki@openedev.com
drivers/mtd/spi-nor/m25p80.c | 2 +- drivers/spi/ich.c | 6 ++---- drivers/spi/spi-uclass.c | 11 ++++------- drivers/spi/ti_qspi.c | 6 +++--- include/spi.h | 14 ++++---------- 5 files changed, 14 insertions(+), 25 deletions(-)
diff --git a/drivers/mtd/spi-nor/m25p80.c b/drivers/mtd/spi-nor/m25p80.c index 7e2702d..58e879c 100644 --- a/drivers/mtd/spi-nor/m25p80.c +++ b/drivers/mtd/spi-nor/m25p80.c @@ -178,7 +178,7 @@ static int m25p80_spi_nor(struct spi_nor *nor) return ret; }
switch (spi->mode_rx) {
switch (spi->mode) { case SPI_RX_SLOW: nor->read_mode = SNOR_READ; break;diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index e543b8f..5f03508 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -678,10 +678,8 @@ static int ich_spi_child_pre_probe(struct udevice *dev) * ICH 7 SPI controller only supports array read command * and byte program command for SST flash */
if (plat->ich_version == PCHV_7) {slave->mode_rx = SPI_RX_SLOW;slave->mode = SPI_TX_BYTE;}
if (plat->ich_version == PCHV_7)slave->mode = SPI_TX_BYTE | SPI_RX_SLOW;
This won't apply. Please rebase this series on top of origin/master. I plan to give a test against this series soon.
return 0;} diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 0dfdd8b..ed6c771 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -181,7 +181,6 @@ static int spi_child_pre_probe(struct udevice *dev)
slave->max_hz = plat->max_hz; slave->mode = plat->mode;
slave->mode_rx = plat->mode_rx; return 0;} @@ -393,7 +392,7 @@ void spi_free_slave(struct spi_slave *slave) int spi_slave_ofdata_to_platdata(const void *blob, int node, struct dm_spi_slave_platdata *plat) {
int mode = 0, mode_rx = 0;
int mode = 0; int value; plat->cs = fdtdec_get_int(blob, node, "reg", -1);@@ -425,24 +424,22 @@ int spi_slave_ofdata_to_platdata(const void *blob, int node, break; }
plat->mode = mode;value = fdtdec_get_uint(blob, node, "spi-rx-bus-width", 1); switch (value) { case 1: break; case 2:mode_rx |= SPI_RX_DUAL;
mode |= SPI_RX_DUAL; break; case 4:
mode_rx |= SPI_RX_QUAD;
mode |= SPI_RX_QUAD; break; default: error("spi-rx-bus-width %d not supported\n", value); break; }
plat->mode_rx = mode_rx;
plat->mode = mode; return 0;} diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index b5c974c..d9d65b4 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -338,7 +338,7 @@ static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv) QSPI_SETUP0_NUM_D_BYTES_8_BITS | QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS);
slave->mode_rx = SPI_RX_QUAD;
slave->mode |= SPI_RX_QUAD;#else memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | @@ -422,7 +422,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, bool enable) { u32 memval;
u32 mode = slave->mode_rx & (SPI_RX_QUAD | SPI_RX_DUAL);
u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL); if (!enable) { writel(0, &priv->base->setup0);@@ -436,7 +436,7 @@ static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv, memval |= QSPI_CMD_READ_QUAD; memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS; memval |= QSPI_SETUP0_READ_QUAD;
slave->mode_rx = SPI_RX_QUAD;
slave->mode |= SPI_RX_QUAD; break; case SPI_RX_DUAL: memval |= QSPI_CMD_READ_DUAL;diff --git a/include/spi.h b/include/spi.h index dd0b11b..61fefa4 100644 --- a/include/spi.h +++ b/include/spi.h @@ -26,12 +26,10 @@ #define SPI_TX_BYTE BIT(8) /* transmit with 1 wire byte */ #define SPI_TX_DUAL BIT(9) /* transmit with 2 wires */ #define SPI_TX_QUAD BIT(10) /* transmit with 4 wires */
-/* SPI mode_rx flags */ -#define SPI_RX_SLOW BIT(0) /* receive with 1 wire slow */ -#define SPI_RX_FAST BIT(1) /* receive with 1 wire fast */ -#define SPI_RX_DUAL BIT(2) /* receive with 2 wires */ -#define SPI_RX_QUAD BIT(3) /* receive with 4 wires */ +#define SPI_RX_SLOW BIT(11) /* receive with 1 wire slow */ +#define SPI_RX_FAST BIT(12) /* receive with 1 wire fast */ +#define SPI_RX_DUAL BIT(13) /* receive with 2 wires */ +#define SPI_RX_QUAD BIT(14) /* receive with 4 wires */
/* SPI bus connection options - see enum spi_dual_flash */ #define SPI_CONN_DUAL_SHARED (1 << 0) @@ -61,13 +59,11 @@ struct dm_spi_bus {
- @cs: Chip select number (0..n-1)
- @max_hz: Maximum bus speed that this slave can tolerate
- @mode: SPI mode to use for this device (see SPI mode flags)
*/
- @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
struct dm_spi_slave_platdata { unsigned int cs; uint max_hz; uint mode;
u8 mode_rx;};
#endif /* CONFIG_DM_SPI */ @@ -94,7 +90,6 @@ struct dm_spi_slave_platdata {
bus (bus->seq) so does not need to be stored- @cs: ID of the chip select connected to the slave.
- @mode: SPI mode to use for this slave (see SPI mode flags)
- @mode_rx: SPI RX mode to use for this slave (see SPI mode_rx flags)
- @wordlen: Size of SPI word in number of bits
- @max_write_size: If non-zero, the maximum number of bytes which can
be written at once, excluding command bytes.@@ -112,7 +107,6 @@ struct spi_slave { unsigned int cs; #endif uint mode;
u8 mode_rx; unsigned int wordlen; unsigned int max_write_size; void *memory_map;--
Regards, Bin