Create new files to handle 2nd generation Chassis as the registers are organized differently.
- Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers.
Signed-off-by: York Sun yorksun@freescale.com Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- arch/powerpc/cpu/mpc85xx/Makefile | 3 +- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 159 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h | 33 +++++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 13 -- arch/powerpc/include/asm/config_mpc85xx.h | 6 + arch/powerpc/include/asm/fsl_serdes.h | 31 +++++ arch/powerpc/include/asm/immap_85xx.h | 5 +- 7 files changed, 235 insertions(+), 15 deletions(-) create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c create mode 100644 arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index da51039..c60320c 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -87,7 +87,8 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o -COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o +COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o +COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o COBJS-$(CONFIG_SECURE_BOOT) += fsl_sfp_snvs.o COBJS-$(CONFIG_CMD_ESBC_VALIDATE) += cmd_esbc_validate.o fsl_validate.o
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c new file mode 100644 index 0000000..b6800c2 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -0,0 +1,159 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/fsl_law.h> +#include <asm/errno.h> +#include "fsl_corenet2_serdes.h" + +static u64 serdes1_prtcl_map; +static u64 serdes2_prtcl_map; +#if defined(CONFIG_PPC_T4240) +static u64 serdes3_prtcl_map; +static u64 serdes4_prtcl_map; +#endif + +#ifdef DEBUG +static const char *serdes_prtcl_str[] = { + [NONE] = "NA", + [PCIE1] = "PCIE1", + [PCIE2] = "PCIE2", + [PCIE3] = "PCIE3", + [PCIE4] = "PCIE4", + [SATA1] = "SATA1", + [SATA2] = "SATA2", + [SRIO1] = "SRIO1", + [SRIO2] = "SRIO2", + [SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1", + [SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2", + [SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3", + [SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4", + [SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5", + [SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1", + [SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2", + [SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3", + [SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4", + [XAUI_FM1] = "XAUI_FM1", + [XAUI_FM2] = "XAUI_FM2", + [AURORA] = "DEBUG", + [CPRI1] = "CPRI1", + [CPRI2] = "CPRI2", + [CPRI3] = "CPRI3", + [CPRI4] = "CPRI4", + [CPRI5] = "CPRI5", + [CPRI6] = "CPRI6", + [CPRI7] = "CPRI7", + [CPRI8] = "CPRI8", + [XAUI_FM1_MAC9] = "XAUI_FM1_MAC9", + [XAUI_FM1_MAC10] = "XAUI_FM1_MAC10", + [XAUI_FM2_MAC9] = "XAUI_FM2_MAC9", + [XAUI_FM2_MAC10] = "XAUI_FM2_MAC10", + [HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9", + [HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10", + [HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9", + [HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10", + [QSGMII_FM1_A] = "QSGMII_FM1_A", + [QSGMII_FM1_B] = "QSGMII_FM1_B", + [QSGMII_FM2_A] = "QSGMII_FM2_A", + [QSGMII_FM2_B] = "QSGMII_FM2_B", + [XFI_FM1_MAC9] = "XFI_FM1_MAC9", + [XFI_FM1_MAC10] = "XFI_FM1_MAC10", + [XFI_FM2_MAC9] = "XFI_FM2_MAC9", + [XFI_FM2_MAC10] = "XFI_FM2_MAC10", + [INTERLAKEN] = "INTERLAKEN", +}; +#endif + +int is_serdes_configured(enum srds_prtcl device) +{ + u64 ret = 0; + + ret |= (1ULL << device) & serdes1_prtcl_map; + ret |= (1ULL << device) & serdes2_prtcl_map; +#if defined(CONFIG_PPC_T4240) + ret |= (1ULL << device) & serdes3_prtcl_map; + ret |= (1ULL << device) & serdes4_prtcl_map; +#endif + + return !!ret; +} + +int serdes_get_first_lane(enum srds_prtcl device) +{ +/* fixme. this is incomplete. */ + return 0; +} + +u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u64 serdes_prtcl_map = 0; + u32 cfg; + int lane; + + cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; + /* Is serdes enabled at all? */ + if (!cfg) { + printf("SERDES%d is not enabled\n", sd); + return 0; + } + + cfg >>= sd_prctl_shift; + printf("Using SERDES%d Protocol: 0x%x\n", sd, cfg); + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd, cfg); + + for (lane = 0; lane < SRDS_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); + serdes_prtcl_map |= (1ULL << lane_prtcl); + } + + return serdes_prtcl_map; +} + +void fsl_serdes_init(void) +{ + + serdes1_prtcl_map = serdes_init(FSL_SRDS_1, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL, + FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT); + serdes2_prtcl_map = serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL, + FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT); +#if defined(CONFIG_PPC_T4240) + serdes3_prtcl_map = serdes_init(FSL_SRDS_3, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL, + FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT); + serdes4_prtcl_map = serdes_init(FSL_SRDS_4, + CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL, + FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT); +#endif + +} diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h new file mode 100644 index 0000000..6529a83 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h @@ -0,0 +1,33 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_CORENET2_SERDES_H +#define __FSL_CORENET2_SERDES_H + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, + FSL_SRDS_3 = 2, + FSL_SRDS_4 = 3, +}; + +int is_serdes_prtcl_valid(int serdes, u32 prtcl); +int serdes_lane_enabled(int lane); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); +#endif /* __FSL_CORENET2_SERDES_H */ diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index 96d14ec..3b9816c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -22,19 +22,6 @@ #ifndef __FSL_CORENET_SERDES_H #define __FSL_CORENET_SERDES_H
-#if defined(CONFIG_PPC_P5040) -/* - * The fourth SerDes bank is on SerDes2, but U-boot currently only supports - * one SerDes controller. For now, pretend that we have three banks and 18 - * lanes. - */ -#define SRDS_MAX_LANES 18 -#define SRDS_MAX_BANK 3 -#else -#define SRDS_MAX_LANES 18 -#define SRDS_MAX_BANK 3 -#endif - enum srds_bank { FSL_SRDS_BANK_1 = 0, FSL_SRDS_BANK_2 = 1, diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0b4a519..fe21b61 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -313,6 +313,7 @@ #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -343,6 +344,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_PPC_P3041) +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -374,6 +376,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_PPC_P3060) +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -397,6 +400,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 8 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -436,6 +440,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 @@ -464,6 +469,7 @@ #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
#elif defined(CONFIG_PPC_P5040) +#define CONFIG_SYS_FSL_QORIQ_CHASSIS1 #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 22525f1..9a7c3a1 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -37,11 +37,17 @@ enum srds_prtcl { SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM2_DTSEC5, + SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC10, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3, @@ -49,6 +55,31 @@ enum srds_prtcl { XAUI_FM1, XAUI_FM2, AURORA, + CPRI1, + CPRI2, + CPRI3, + CPRI4, + CPRI5, + CPRI6, + CPRI7, + CPRI8, + XAUI_FM1_MAC9, + XAUI_FM1_MAC10, + XAUI_FM2_MAC9, + XAUI_FM2_MAC10, + HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, + HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, + QSGMII_FM1_A, /* A indicates MACs 1-4 */ + QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ + QSGMII_FM2_A, + QSGMII_FM2_B, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + XFI_FM2_MAC9, + XFI_FM2_MAC10, + INTERLAKEN, };
int is_serdes_configured(enum srds_prtcl device); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 783bc28..020475b 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2426,6 +2426,8 @@ typedef struct ccsr_gur {
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define MAX_SERDES 4 +#define SRDS_MAX_LANES 8 +#define SRDS_MAX_BANK 2 typedef struct serdes_corenet { struct { u32 rstctl; /* Reset Control Register */ @@ -2476,7 +2478,6 @@ typedef struct serdes_corenet { } srdslnpssr[8]; u8 res_200[0x800-0x200]; struct { -/* fixme: Document is wrong here */ u32 gcr0; /* 0x800 General Control Register 0 */ u32 gcr1; /* 0x804 General Control Register 1 */ u32 gcr2; /* 0x808 General Control Register 2 */ @@ -2493,6 +2494,8 @@ typedef struct serdes_corenet {
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define SRDS_MAX_LANES 18 +#define SRDS_MAX_BANK 3 typedef struct serdes_corenet { struct { u32 rstctl; /* Reset Control Register */