Signed-off-by: Alison Wang b18965@freescale.com --- arch/m68k/cpu/mcf547x_8x/cpu.c | 38 +++++++------- arch/m68k/cpu/mcf547x_8x/cpu_init.c | 84 +++++++++++++++++---------------- arch/m68k/cpu/mcf547x_8x/interrupts.c | 15 +++--- arch/m68k/cpu/mcf547x_8x/pci.c | 59 ++++++++++++----------- arch/m68k/cpu/mcf547x_8x/slicetimer.c | 38 ++++++++------- board/freescale/m547xevb/m547xevb.c | 34 +++++++------ board/freescale/m548xevb/m548xevb.c | 34 +++++++------ 7 files changed, 158 insertions(+), 144 deletions(-)
diff --git a/arch/m68k/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c index 7590f2c..157a8e4 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -31,19 +31,20 @@ #include <netdev.h>
#include <asm/immap.h> +#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- gptmr->pre = 10; - gptmr->cnt = 1; + out_be16(&gptmr->pre, 10); + out_be16(&gptmr->cnt, 1);
/* enable watchdog, set timeout to 0 and wait */ - gptmr->mode = GPT_TMS_SGPIO; - gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE; + out_8(&gptmr->mode, GPT_TMS_SGPIO); + out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
/* we don't return! */ return 1; @@ -51,12 +52,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
int checkcpu(void) { - volatile siu_t *siu = (siu_t *) MMAP_SIU; + siu_t *siu = (siu_t *) MMAP_SIU; u16 id = 0;
puts("CPU: ");
- switch ((siu->jtagid & 0x000FF000) >> 12) { + switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) { case 0x0C: id = 5485; break; @@ -111,18 +112,18 @@ int checkcpu(void) /* Called by macro WATCHDOG_RESET */ void hw_watchdog_reset(void) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- gptmr->ocpw = 0xa5; + out_8(&gptmr->ocpw, 0xa5); }
int watchdog_disable(void) { - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ - gptmr->mode = 0; - gptmr->ctrl = 0; + out_8(&gptmr->mode, 0); + out_8(&gptmr->ctrl, 0);
puts("WATCHDOG:disabled\n");
@@ -131,14 +132,13 @@ int watchdog_disable(void)
int watchdog_init(void) { + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT); + out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
- gptmr->pre = CONFIG_WATCHDOG_TIMEOUT; - gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000; - - gptmr->mode = GPT_TMS_SGPIO; - gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN; + out_8(&gptmr->mode, GPT_TMS_SGPIO); + out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN); puts("WATCHDOG:enabled\n");
return (0); diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c b/arch/m68k/cpu/mcf547x_8x/cpu_init.c index 60c9126..4eb8a7c 100644 --- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c +++ b/arch/m68k/cpu/mcf547x_8x/cpu_init.c @@ -3,7 +3,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <MCD_dma.h> #include <asm/immap.h> +#include <asm/io.h>
#if defined(CONFIG_CMD_NET) #include <config.h> @@ -44,58 +45,59 @@ */ void cpu_init_f(void) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; - volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
- xlbarb->adrto = 0x2000; - xlbarb->datto = 0x2500; - xlbarb->busto = 0x3000; + out_be32(&xlbarb->adrto, 0x2000); + out_be32(&xlbarb->datto, 0x2500); + out_be32(&xlbarb->busto, 0x3000);
- xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT; + out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
/* Master Priority Enable */ - xlbarb->prien = 0xff; - xlbarb->pri = 0; + out_be32(&xlbarb->prien, 0xff); + out_be32(&xlbarb->pri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL)) - fbcs->csar0 = CONFIG_SYS_CS0_BASE; - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL; - fbcs->csmr0 = CONFIG_SYS_CS0_MASK; + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE); + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL); + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK); #endif
#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL)) - fbcs->csar1 = CONFIG_SYS_CS1_BASE; - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL; - fbcs->csmr1 = CONFIG_SYS_CS1_MASK; + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE); + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL); + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK); #endif
#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL)) - fbcs->csar2 = CONFIG_SYS_CS2_BASE; - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL; - fbcs->csmr2 = CONFIG_SYS_CS2_MASK; + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE); + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL); + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK); #endif
#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL)) - fbcs->csar3 = CONFIG_SYS_CS3_BASE; - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL; - fbcs->csmr3 = CONFIG_SYS_CS3_MASK; + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE); + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL); + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK); #endif
#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL)) - fbcs->csar4 = CONFIG_SYS_CS4_BASE; - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL; - fbcs->csmr4 = CONFIG_SYS_CS4_MASK; + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE); + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL); + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK); #endif
#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL)) - fbcs->csar5 = CONFIG_SYS_CS5_BASE; - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL; - fbcs->csmr5 = CONFIG_SYS_CS5_MASK; + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE); + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL); + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK); #endif
#ifdef CONFIG_FSL_I2C - gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; + out_be16(&gpio->par_feci2cirq, + GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA); #endif
icache_enable(); @@ -115,44 +117,44 @@ int cpu_init_r(void)
void uart_port_conf(int port) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; - volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); + gpio_t *gpio = (gpio_t *) MMAP_GPIO; + u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
/* Setup Ports: */ switch (port) { case 0: - gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); + out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); break; case 1: - gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); + out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); break; case 2: - gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); + out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); break; case 3: - gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); + out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); break; }
- *pscsicr &= 0xF8; + clrbits_8(pscsicr, 0x07); }
#if defined(CONFIG_CMD_NET) int fecpin_setclear(struct eth_device *dev, int setclear) { - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + gpio_t *gpio = (gpio_t *) MMAP_GPIO; struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
if (setclear) { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq |= 0xF000; + setbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq |= 0x0FC0; + setbits_be16(&gpio->par_feci2cirq, 0x0fc0); } else { if (info->iobase == CONFIG_SYS_FEC0_IOBASE) - gpio->par_feci2cirq &= 0x0FFF; + clrbits_be16(&gpio->par_feci2cirq, 0xf000); else - gpio->par_feci2cirq &= 0xF03F; + clrbits_be16(&gpio->par_feci2cirq, 0x0fc0); } return 0; } diff --git a/arch/m68k/cpu/mcf547x_8x/interrupts.c b/arch/m68k/cpu/mcf547x_8x/interrupts.c index 76be876..d215438 100644 --- a/arch/m68k/cpu/mcf547x_8x/interrupts.c +++ b/arch/m68k/cpu/mcf547x_8x/interrupts.c @@ -1,6 +1,6 @@ /* * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,14 +25,15 @@ /* CPU specific interrupt routine */ #include <common.h> #include <asm/immap.h> +#include <asm/io.h>
int interrupt_init(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */ - intp->imrh0 |= 0xFFFFFFFF; - intp->imrl0 |= 0xFFFFFFFF; + setbits_be32(&intp->imrh0, 0xffffffff); + setbits_be32(&intp->imrl0, 0xffffffff);
enable_interrupts();
@@ -42,9 +43,9 @@ int interrupt_init(void) #if defined(CONFIG_SLTTMR) void dtimer_intr_setup(void) { - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI; - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK; + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI); + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK); } #endif diff --git a/arch/m68k/cpu/mcf547x_8x/pci.c b/arch/m68k/cpu/mcf547x_8x/pci.c index f867dc1..1a81e3f 100644 --- a/arch/m68k/cpu/mcf547x_8x/pci.c +++ b/arch/m68k/cpu/mcf547x_8x/pci.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -88,53 +88,56 @@ int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev,
void pci_mcf547x_8x_init(struct pci_controller *hose) { - volatile pci_t *pci = (volatile pci_t *) MMAP_PCI; - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + pci_t *pci = (pci_t *) MMAP_PCI; + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Port configuration */ - gpio->par_pcibg = - GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | - GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | - GPIO_PAR_PCIBG_PCIBG4(3); - gpio->par_pcibr = - GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | - GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | - GPIO_PAR_PCIBR_PCIBR4(3); + out_be16(&gpio->par_pcibg, + GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | + GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | + GPIO_PAR_PCIBG_PCIBG4(3)); + out_be16(&gpio->par_pcibr, + GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | + GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | + GPIO_PAR_PCIBR_PCIBR4(3));
/* Assert reset bit */ - pci->gscr |= PCI_GSCR_PR; + setbits_be32(&pci->gscr, PCI_GSCR_PR);
- pci->tcr1 = PCI_TCR1_P; + out_be32(&pci->tcr1, PCI_TCR1_P);
/* Initiator windows */ - pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16); - pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16); - pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16); + out_be32(&pci->iw0btar, + CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); + out_be32(&pci->iw1btar, + CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); + out_be32(&pci->iw2btar, + CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
- pci->iwcr = - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + out_be32(&pci->iwcr, + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
- pci->icr = 0; + out_be32(&pci->icr, 0);
/* Enable bus master and mem access */ - pci->scr = PCI_SCR_B | PCI_SCR_M; + out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
/* Cache line size and master latency */ - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); - pci->cr2 = 0; + out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8)); + out_be32(&pci->cr2, 0);
#ifdef CONFIG_SYS_PCI_BAR0 - pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0); - pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN; + out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); + out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); #endif #ifdef CONFIG_SYS_PCI_BAR1 - pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1); - pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN; + out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); + out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); #endif
/* Deassert reset bit */ - pci->gscr &= ~PCI_GSCR_PR; + clrbits_be32(&pci->gscr, PCI_GSCR_PR); udelay(1000);
/* Enable PCI bus master support */ diff --git a/arch/m68k/cpu/mcf547x_8x/slicetimer.c b/arch/m68k/cpu/mcf547x_8x/slicetimer.c index ee2e35b..25dd2ae 100644 --- a/arch/m68k/cpu/mcf547x_8x/slicetimer.c +++ b/arch/m68k/cpu/mcf547x_8x/slicetimer.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 Freescale Semiconductor, Inc. + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@
#include <asm/timer.h> #include <asm/immap.h> +#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -42,31 +43,32 @@ extern void dtimer_intr_setup(void);
void __udelay(unsigned long usec) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE); u32 now, freq;
/* 1 us period */ freq = CONFIG_SYS_TIMER_PRESCALER;
- timerp->cr = 0; /* Disable */ - timerp->tcnt = usec * freq; - timerp->cr = SLT_CR_TEN; + /* Disable */ + out_be32(&timerp->cr, 0); + out_be32(&timerp->tcnt, usec * freq); + out_be32(&timerp->cr, SLT_CR_TEN);
- now = timerp->cnt; + now = in_be32(&timerp->cnt); while (now != 0) - now = timerp->cnt; + now = in_be32(&timerp->cnt);
- timerp->sr |= SLT_SR_ST; - timerp->cr = 0; + setbits_be32(&timerp->sr, SLT_SR_ST); + out_be32(&timerp->cr, 0); }
void dtimer_interrupt(void *not_used) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
/* check for timer interrupt asserted */ if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { - timerp->sr |= SLT_SR_ST; + setbits_be32(&timerp->sr, SLT_SR_ST); timestamp++; return; } @@ -74,25 +76,27 @@ void dtimer_interrupt(void *not_used)
int timer_init(void) { - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE); + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
timestamp = 0;
- timerp->cr = 0; /* disable timer */ - timerp->tcnt = 0; - timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */ + /* disable timer */ + out_be32(&timerp->cr, 0); + out_be32(&timerp->tcnt, 0); + /* clear status */ + out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
/* initialize and enable timer interrupt */ irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
/* Interrupt every ms */ - timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER; + out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
dtimer_intr_setup();
/* set a period of 1us, set timer mode to restart and enable timer and interrupt */ - timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN; + out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN); return 0; }
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c index 9f1ec38..fd9bddd 100644 --- a/board/freescale/m547xevb/m547xevb.c +++ b/board/freescale/m547xevb/m547xevb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,14 +41,14 @@ int checkboard(void)
phys_size_t initdram(int board_type) { - volatile siu_t *siu = (siu_t *) (MMAP_SIU); - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + siu_t *siu = (siu_t *) (MMAP_SIU); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; #ifdef CONFIG_SYS_DRAMSZ1 u32 temp; #endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -55,7 +56,7 @@ phys_size_t initdram(int board_type) break; } i--; - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1 temp = CONFIG_SYS_DRAMSZ1 * 0x100000; @@ -65,31 +66,32 @@ phys_size_t initdram(int board_type) } i--; dramsize += temp; - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); #endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c index fbc0888..fb216d8 100644 --- a/board/freescale/m548xevb/m548xevb.c +++ b/board/freescale/m548xevb/m548xevb.c @@ -2,7 +2,7 @@ * (C) Copyright 2000-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -28,6 +28,7 @@ #include <common.h> #include <pci.h> #include <asm/immap.h> +#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,14 +41,14 @@ int checkboard(void)
phys_size_t initdram(int board_type) { - volatile siu_t *siu = (siu_t *) (MMAP_SIU); - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM); + siu_t *siu = (siu_t *) (MMAP_SIU); + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM); u32 dramsize, i; #ifdef CONFIG_SYS_DRAMSZ1 u32 temp; #endif
- siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH; + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
dramsize = CONFIG_SYS_DRAMSZ * 0x100000; for (i = 0x13; i < 0x20; i++) { @@ -55,7 +56,7 @@ phys_size_t initdram(int board_type) break; } i--; - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i); + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
#ifdef CONFIG_SYS_DRAMSZ1 temp = CONFIG_SYS_DRAMSZ1 * 0x100000; @@ -65,31 +66,32 @@ phys_size_t initdram(int board_type) } i--; dramsize += temp; - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i); + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i); #endif
- sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1; - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2; + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1); + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
/* Issue PALL */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Issue LEMR */ - sdram->mode = CONFIG_SYS_SDRAM_EMOD; - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD); + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
udelay(500);
/* Issue PALL */ - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
/* Perform two refresh cycles */ - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4; + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4); + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
- sdram->mode = CONFIG_SYS_SDRAM_MODE; + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
- sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00; + out_be32(&sdram->ctrl, + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
udelay(100);