On Wed, Aug 01, 2018 at 05:26:10PM -0600, Stephen Warren wrote:
On 07/31/2018 12:38 PM, Stephen Warren wrote:
From: Stephen Warren swarren@nvidia.com
Align the size of the carveout region to 2M. This ensures that the size can be accurately represented by an LPAE page table that uses sections.
This solves a bug (hang at boot time soon after printing the DRAM size) that only shows up when the following two commits are merged together: d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported 6e584e633d10 ARM: tegra: avoid using secure carveout RAM
Cc: Mark Kettenis kettenis@openbsd.org Cc: Alexander Graf agraf@suse.de Signed-off-by: Stephen Warren swarren@nvidia.com
This should be applied quickly since it fixes a regression that causes all boots to fail, which in turn causes test/py to reset and "reflash" the target board for each test, which causes the test to take eons.
Could we apply this please? My Jenkins system will love you because of it:-)
I'm looking for one more person to Ack this, thanks!