On Thu, Jun 16, 2016 at 10:10 PM, Bin Meng bmeng.cn@gmail.com wrote:
Hi George,
On Wed, Jun 15, 2016 at 10:51 PM, George McCollister george.mccollister@gmail.com wrote:
Add support for Advantech SOM-DB5800 with the SOM-6867 installed. This is very similar to conga-qeval20-qa3-e3845 in that there is a reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867) installed.
Currently supported:
- 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on SOM-DB5800.
- 4x USB 2.0 (EHCI)
- Video
- SATA
- Ethernet
- PCIe
- Realtek ALC892 HD Audio Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO HDA_SDI0 is set in DT to enable HD Audio codec. Pin defaults for codec pin complexs are not changed.
Not supported:
- Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
- USB 3.0 (XHCI)
- TPM
Signed-off-by: George McCollister george.mccollister@gmail.com
arch/x86/Kconfig | 4 + arch/x86/dts/Makefile | 3 +- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 299 +++++++++++++++++++++ board/advantech/Kconfig | 28 ++ board/advantech/som-db5800-som-6867/.gitignore | 3 + board/advantech/som-db5800-som-6867/Kconfig | 28 ++ board/advantech/som-db5800-som-6867/MAINTAINERS | 7 + board/advantech/som-db5800-som-6867/Makefile | 8 + .../som-db5800-som-6867/acpi/mainboard.asl | 11 + board/advantech/som-db5800-som-6867/dsdt.asl | 14 + .../som-db5800-som-6867/som-db5800-som-6867.c | 28 ++ board/advantech/som-db5800-som-6867/start.S | 9 + configs/som-db5800-som-6867_defconfig | 61 +++++ include/configs/som-db5800-som-6867.h | 41 +++ 14 files changed, 543 insertions(+), 1 deletion(-) create mode 100644 arch/x86/dts/baytrail_som-db5800-som-6867.dts create mode 100644 board/advantech/Kconfig create mode 100644 board/advantech/som-db5800-som-6867/.gitignore create mode 100644 board/advantech/som-db5800-som-6867/Kconfig create mode 100644 board/advantech/som-db5800-som-6867/MAINTAINERS create mode 100644 board/advantech/som-db5800-som-6867/Makefile create mode 100644 board/advantech/som-db5800-som-6867/acpi/mainboard.asl create mode 100644 board/advantech/som-db5800-som-6867/dsdt.asl create mode 100644 board/advantech/som-db5800-som-6867/som-db5800-som-6867.c create mode 100644 board/advantech/som-db5800-som-6867/start.S create mode 100644 configs/som-db5800-som-6867_defconfig create mode 100644 include/configs/som-db5800-som-6867.h
Generally looks good. Some comments below.
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 29d2307..29d1120 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -8,6 +8,9 @@ choice prompt "Mainboard vendor" default VENDOR_EMULATION
+config VENDOR_ADVANTECH
bool "advantech"config VENDOR_CONGATEC bool "congatec"
@@ -29,6 +32,7 @@ config VENDOR_INTEL endchoice
# board-specific options below +source "board/advantech/Kconfig" source "board/congatec/Kconfig" source "board/coreboot/Kconfig" source "board/efi/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 23156bb..4f07f41 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -14,7 +14,8 @@ dtb-y += bayleybay.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \
broadwell_som-6896.dtb
broadwell_som-6896.dtb \baytrail_som-db5800-som-6867.dtbtargets += $(dtb-y)
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts new file mode 100644 index 0000000..e4df151 --- /dev/null +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -0,0 +1,299 @@ +/*
- Copyright (C) 2014, Bin Meng bmeng.cn@gmail.com
- Copyright (C) 2016, George McCollister george.mccollister@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/;
+#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h>
+/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi"
+/ {
model = "Advantech SOM-DB5800-SOM-6867";compatible = "advantech,som-db5800-som-6867", "intel,baytrail";aliases {serial0 = &serial;spi0 = &spi;};config {silent_console = <0>;};pch_pinctrl {compatible = "intel,x86-pinctrl";reg = <0 0>;/* HDA_RSTB */soc_gpio_s0_8@0 {gpio-offset = <0x0 8>;gpio-offset property is not needed as it is initialized to native function mode other than gpio.
Okay, I'll remove them.
pad-offset = <0x220>;mode-func = <2>;};/* HDA_SYNC */soc_gpio_s0_9@0 {gpio-offset = <0x0 9>;pad-offset = <0x250>;mode-func = <2>;pull-assign = <1>;};/* HDA_CLK */soc_gpio_s0_10@0 {gpio-offset = <0x0 10>;pad-offset = <0x240>;mode-func = <2>;};/* HDA_SDO */soc_gpio_s0_11@0 {gpio-offset = <0x0 11>;pad-offset = <0x260>;mode-func = <2>;pull-assign = <1>;};/* HDA_SDI0 */soc_gpio_s0_12@0 {gpio-offset = <0x0 12>;pad-offset = <0x270>;mode-func = <2>;};What about the sdmmc3_cd pin? Is there any SD slot on the board that is connected to the SD controller?
The datasheet makes no mention of bringing SD to the COM Express connector so I'm going to disable it in v2.
};chosen {stdout-path = "/serial";};cpus {#address-cells = <1>;#size-cells = <0>;cpu@0 {device_type = "cpu";compatible = "intel,baytrail-cpu";reg = <0>;intel,apic-id = <0>;};cpu@1 {device_type = "cpu";compatible = "intel,baytrail-cpu";reg = <1>;intel,apic-id = <2>;};cpu@2 {device_type = "cpu";compatible = "intel,baytrail-cpu";reg = <2>;intel,apic-id = <4>;};cpu@3 {device_type = "cpu";compatible = "intel,baytrail-cpu";reg = <3>;intel,apic-id = <6>;};};pci {compatible = "intel,pci-baytrail", "pci-x86";#address-cells = <3>;#size-cells = <2>;u-boot,dm-pre-reloc;ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x400000000x42000000 0x0 0xc0000000 0xc0000000 0 0x200000000x01000000 0x0 0x2000 0x2000 0 0xe000>;pch@1f,0 {reg = <0x0000f800 0 0 0 0>;compatible = "pci8086,0f1c", "intel,pch9";#address-cells = <1>;#size-cells = <1>;irq-router {compatible = "intel,irq-router";intel,pirq-config = "ibase";intel,ibase-offset = <0x50>;intel,actl-addr = <0>;intel,pirq-link = <8 8>;intel,pirq-mask = <0xdee0>;intel,pirq-routing = </* BayTrail PCI devices */PCI_BDF(0, 2, 0) INTA PIRQAPCI_BDF(0, 3, 0) INTA PIRQAPCI_BDF(0, 16, 0) INTA PIRQAPCI_BDF(0, 17, 0) INTA PIRQAPCI_BDF(0, 18, 0) INTA PIRQAPCI_BDF(0, 19, 0) INTA PIRQAPCI_BDF(0, 20, 0) INTA PIRQAPCI_BDF(0, 21, 0) INTA PIRQAPCI_BDF(0, 22, 0) INTA PIRQAPCI_BDF(0, 23, 0) INTA PIRQAPCI_BDF(0, 24, 0) INTA PIRQAPCI_BDF(0, 24, 1) INTC PIRQCPCI_BDF(0, 24, 2) INTD PIRQDPCI_BDF(0, 24, 3) INTB PIRQBPCI_BDF(0, 24, 4) INTA PIRQAPCI_BDF(0, 24, 5) INTC PIRQCPCI_BDF(0, 24, 6) INTD PIRQDPCI_BDF(0, 24, 7) INTB PIRQBPCI_BDF(0, 26, 0) INTA PIRQAPCI_BDF(0, 27, 0) INTA PIRQAPCI_BDF(0, 28, 0) INTA PIRQAPCI_BDF(0, 28, 1) INTB PIRQBPCI_BDF(0, 28, 2) INTC PIRQCPCI_BDF(0, 28, 3) INTD PIRQDPCI_BDF(0, 29, 0) INTA PIRQAPCI_BDF(0, 30, 0) INTA PIRQAPCI_BDF(0, 30, 1) INTD PIRQDPCI_BDF(0, 30, 2) INTB PIRQBPCI_BDF(0, 30, 3) INTC PIRQCPCI_BDF(0, 30, 4) INTD PIRQDPCI_BDF(0, 30, 5) INTB PIRQBPCI_BDF(0, 31, 3) INTB PIRQB/** PCIe root ports downstream* interrupts*/PCI_BDF(1, 0, 0) INTA PIRQAPCI_BDF(1, 0, 0) INTB PIRQBPCI_BDF(1, 0, 0) INTC PIRQCPCI_BDF(1, 0, 0) INTD PIRQDPCI_BDF(2, 0, 0) INTA PIRQBPCI_BDF(2, 0, 0) INTB PIRQCPCI_BDF(2, 0, 0) INTC PIRQDPCI_BDF(2, 0, 0) INTD PIRQAPCI_BDF(3, 0, 0) INTA PIRQCPCI_BDF(3, 0, 0) INTB PIRQDPCI_BDF(3, 0, 0) INTC PIRQAPCI_BDF(3, 0, 0) INTD PIRQBPCI_BDF(4, 0, 0) INTA PIRQDPCI_BDF(4, 0, 0) INTB PIRQAPCI_BDF(4, 0, 0) INTC PIRQBPCI_BDF(4, 0, 0) INTD PIRQC>;};spi: spi {#address-cells = <1>;#size-cells = <0>;compatible = "intel,ich9-spi";spi-flash@0 {#address-cells = <1>;#size-cells = <1>;reg = <0>;compatible = "macronix,mx25l6405d","spi-flash";memory-map = <0xff800000 0x00800000>;rw-mrc-cache {label = "rw-mrc-cache";reg = <0x006f0000 0x00010000>;};};};gpioa {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0 0x20>;bank-name = "A";};gpiob {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x20 0x20>;bank-name = "B";};gpioc {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x40 0x20>;bank-name = "C";};gpiod {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x60 0x20>;bank-name = "D";};gpioe {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x80 0x20>;bank-name = "E";};gpiof {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0xA0 0x20>;bank-name = "F";};};};fsp {compatible = "intel,baytrail-fsp";fsp,mrc-init-tseg-size = <0>;fsp,mrc-init-mmio-size = <0x800>;fsp,mrc-init-spd-addr1 = <0xa0>;fsp,mrc-init-spd-addr2 = <0xa2>;fsp,emmc-boot-mode = <1>;fsp,enable-sdio;fsp,enable-sdcard;fsp,enable-spi;fsp,enable-sata;fsp,sata-mode = <1>;fsp,enable-azalia;fsp,lpss-sio-enable-pci-mode;fsp,enable-dma0;fsp,enable-dma1;fsp,enable-i2c0;fsp,enable-i2c1;fsp,enable-i2c2;fsp,enable-i2c3;fsp,enable-i2c4;fsp,enable-i2c5;fsp,enable-i2c6;fsp,enable-pwm0;fsp,enable-pwm1;fsp,igd-dvmt50-pre-alloc = <2>;fsp,aperture-size = <2>;fsp,gtt-size = <2>;fsp,scc-enable-pci-mode;fsp,os-selection = <4>;fsp,emmc45-ddr50-enabled;fsp,emmc45-retune-timer-value = <8>;fsp,enable-igd;fsp,serial-debug-port-address = <0x3f8>;fsp,serial-debug-port-type = <1>;};microcode {update@0 {+#include "microcode/m0130673325.dtsi"
};update@1 {+#include "microcode/m0130679907.dtsi"
};};+}; diff --git a/board/advantech/Kconfig b/board/advantech/Kconfig new file mode 100644 index 0000000..a8d4969 --- /dev/null +++ b/board/advantech/Kconfig @@ -0,0 +1,28 @@ +if VENDOR_ADVANTECH
+choice
prompt "Mainboard model"optional+config TARGET_SOM_DB5800_SOM_6867
bool "Advantech SOM-DB5800 & SOM-6867"helpAdvantech SOM-DB5800 COM Express development board with SOM-6867installed.SOM-6867 is a COM Express Type 6 Compact Module with either an IntelAtom E3845 or Celeron N2920 processor.SOM-DB5800 is a COM Express Development board with:10/100/1000 EthernetPCIe slots4x USB portsHDMI/DisplayPort/DVI, LVDS, VGASATA portsALC892 HD Audio Codec+endchoice
+source "board/advantech/som-db5800-som-6867/Kconfig"
+endif diff --git a/board/advantech/som-db5800-som-6867/.gitignore b/board/advantech/som-db5800-som-6867/.gitignore new file mode 100644 index 0000000..6eb8a54 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig new file mode 100644 index 0000000..f6f3748 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -0,0 +1,28 @@ +if TARGET_SOM_DB5800_SOM_6867
+config SYS_BOARD
default "som-db5800-som-6867"+config SYS_VENDOR
default "advantech"+config SYS_SOC
default "baytrail"+config SYS_CONFIG_NAME
default "som-db5800-som-6867"+config SYS_TEXT_BASE
default 0xfff00000 if !EFI_STUBdefault 0x01110000 if EFI_STUB+config BOARD_SPECIFIC_OPTIONS # dummy
def_bool yselect X86_RESET_VECTOR if !EFI_STUBselect INTEL_BAYTRAILselect BOARD_ROMSIZE_KB_8192+config PCIE_ECAM_BASE
default 0xe0000000+endif diff --git a/board/advantech/som-db5800-som-6867/MAINTAINERS b/board/advantech/som-db5800-som-6867/MAINTAINERS new file mode 100644 index 0000000..92989bf --- /dev/null +++ b/board/advantech/som-db5800-som-6867/MAINTAINERS @@ -0,0 +1,7 @@ +Advantech SOM-DB5800-SOM-6867 +M: George McCollister george.mccollister@gmail.com +S: Maintained +F: board/advantech/som-db5800-som-6867 +F: include/configs/som-db5800-som-6867.h +F: configs/som-db5800-som-6867_defconfig +F: arch/x86/dts/baytrail_som-db5800-som-6867.dts diff --git a/board/advantech/som-db5800-som-6867/Makefile b/board/advantech/som-db5800-som-6867/Makefile new file mode 100644 index 0000000..9837aa0 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += som-db5800-som-6867.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/advantech/som-db5800-som-6867/acpi/mainboard.asl b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/*
- Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/* Power Button */ +Device (PWRB) +{
Name(_HID, EISAID("PNP0C0C"))+} diff --git a/board/advantech/som-db5800-som-6867/dsdt.asl b/board/advantech/som-db5800-som-6867/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/dsdt.asl @@ -0,0 +1,14 @@ +/*
- Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{
/* platform specific */#include <asm/arch/acpi/platform.asl>/* board specific */#include "acpi/mainboard.asl"+} diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c new file mode 100644 index 0000000..73bb565 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -0,0 +1,28 @@ +/*
- Copyright (C) 2016 Stefan Roese sr@denx.de
- Copyright (C) 2016 George McCollister george.mccollister@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <winbond_w83627.h> +#include <asm/gpio.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h>
I believe the above 4 header files are not needed.
I'll remove them.
+int board_early_init_f(void) +{
/** The FSP enables the BayTrail internal legacy UART (again).* Disable it again, so that the one on the EC can be used.*/setup_internal_uart(0);Which UART is this board using? The codes disables the internal UART
The UARTs are provided by an LPC connected ITE branded EC. I forget which exact model (it's under the heatspreader and I'd rather not disassemble it at the moment). It had no publicly available datasheet, I might have been able to get it if I contacted ITE and signed an NDA.
and the comment says the one on the EC? Does that mean the UART on the EC comes out of reset as enabled and no software programming is needed (to turn it on, and set its IRQ to IRQ4)?
Correct, the first UART on the EC comes out of reset as enabled set the IRQ4. The second UART on the EC comes out of reset as enabled set to IRQ3. Standard PC COM1 and COM2.
return 0;+}
+int arch_early_init_r(void) +{
return 0;+} diff --git a/board/advantech/som-db5800-som-6867/start.S b/board/advantech/som-db5800-som-6867/start.S new file mode 100644 index 0000000..2c941a4 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/start.S @@ -0,0 +1,9 @@ +/*
- Copyright (C) 2015, Google, Inc
- SPDX-License-Identifier: GPL-2.0+
- */
+.globl early_board_init +early_board_init:
jmp early_board_init_retdiff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig new file mode 100644 index 0000000..60a1558 --- /dev/null +++ b/configs/som-db5800-som-6867_defconfig @@ -0,0 +1,61 @@ +CONFIG_X86=y +CONFIG_VENDOR_ADVANTECH=y +CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867" +CONFIG_TARGET_SOM_DB5800_SOM_6867=y +CONFIG_HAVE_INTEL_ME=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y +CONFIG_SEABIOS=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h new file mode 100644 index 0000000..0ed816c --- /dev/null +++ b/include/configs/som-db5800-som-6867.h @@ -0,0 +1,41 @@ +/*
- Copyright (C) 2015 Google, Inc
- SPDX-License-Identifier: GPL-2.0+
- */
+/*
- board/config.h - configuration options, board specific
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#include <configs/x86-common.h>
+#define CONFIG_SYS_MONITOR_LEN (1 << 20) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_PCI_PNP +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \
"stdout=serial,vga\0" \"stderr=serial,vga\0"+#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}+#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC_SDMA
+#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x006ef000
+#endif /* __CONFIG_H */
Regards, Bin