MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write through cache on E6500. L2 cache is enabled to to hold the data. This patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.
Signed-off-by: York Sun yorksun@freescale.com Reported-by: Jeffery Zhu Jefferry.Zhu@freescale.com
---
arch/powerpc/cpu/mpc85xx/start.S | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index a70fb71..d867e2a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1116,7 +1116,11 @@ switch_as: li r0,0 1: dcbz r0,r3 - dcbtls 0,r0,r3 +#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */ + dcbtls 2, r0, r3 +#else + dcbtls 0, r0, r3 +#endif addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b
@@ -1727,7 +1731,11 @@ unlock_ram_in_cache: slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 1: dcbi r0,r3 +#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */ + dcblc 2, r0, r3 +#else dcblc r0,r3 +#endif addi r3,r3,CONFIG_SYS_CACHELINE_SIZE bdnz 1b sync