2 Nov
2015
2 Nov
'15
10:39 p.m.
On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek michal.simek@xilinx.com wrote:
Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47
Isn't it dependent on which board and what the clock setup is? Should this be specified by the board?
which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31).
Signed-off-by: Michal Simek michal.simek@xilinx.com
Acked-by: Joe Hershberger joe.hershberger@ni.com