Hi Fabio,
On 08/29/2016 04:37 PM, Fabio Estevam wrote:
From: Fabio Estevam fabio.estevam@nxp.com
Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table.
Signed-off-by: Fabio Estevam fabio.estevam@nxp.com
Changes since v3:
- None
board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 2ca0921..9243ec5 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -779,17 +779,17 @@ static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { .dram_odt0 = 0x00000030, .dram_odt1 = 0x00000030, .dram_sdba2 = 0x00000000,
- .dram_sdclk_0 = 0x00000008,
- .dram_sdqs0 = 0x00000038,
- .dram_sdclk_0 = 0x00000030,
- .dram_sdqs0 = 0x00000030, .dram_sdqs1 = 0x00000030, .dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x00070007,
- .p0_mpdgctrl0 = 0x41490145,
- .p0_mprddlctl = 0x40404546,
- .p0_mpwrdlctl = 0x4040524D,
Hmmm. I don't think I've ever seen a value of zero for dectrl0, but it does match the DCD.
When time permits, I'll try running the DDR stress tool on my EVK and also see what it takes to get the mx6memcal rig to run on the 6UL.
- .p0_mpwldectrl0 = 0x00000000,
- .p0_mpdgctrl0 = 0x41570155,
- .p0_mprddlctl = 0x4040474A,
- .p0_mpwrdlctl = 0x40405550,
};
struct mx6_ddr_sysinfo ddr_sysinfo = { @@ -799,7 +799,7 @@ struct mx6_ddr_sysinfo ddr_sysinfo = { .cs1_mirror = 0, .rtt_wr = 2, .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
- .walat = 1, /* Write additional latency */
- .walat = 0, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */
Reviewed-by: Eric Nelson eric@nelint.com