On Fri, Jul 12, 2013 at 11:08 AM, Lukasz Majewski l.majewski@samsung.comwrote:
Provide proper setting for the APLL fout frequency calculation for Exynos4 based targets (especially Exynos4210 - Trats board).
Signed-off-by: Lukasz Majewski l.majewski@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com
This also fixes booting on snow.
Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org
arch/arm/cpu/armv7/exynos/clock.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 9f07181..5a5cfa1 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -141,18 +141,17 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k) fout = (m + k / div) * (freq / (p * (1 << s))); } else { /*
* Exynos4210
* Exynos4412 / Exynos5250 * FOUT = MDIV * FIN / (PDIV * 2^SDIV) *
* Exynos4412 / Exynos5250
* Exynos4210 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1)) */ if (proid_is_exynos4210())
fout = m * (freq / (p * (1 << s)));else fout = m * (freq / (p * (1 << (s - 1))));
elsefout = m * (freq / (p * (1 << s))); }
return fout;}
-- 1.7.10.4
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