At present these settings are in the node for host-bridge and so are visible in TPL as well as SPL. But they are only used for SPL.
Move them to a subnode so that TPL does not included them.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/apollolake/fsp_m.c | 5 ++++- arch/x86/dts/chromebook_coral.dts | 5 +++++ 2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/apollolake/fsp_m.c b/arch/x86/cpu/apollolake/fsp_m.c index cef937573b0..c6be707e4ea 100644 --- a/arch/x86/cpu/apollolake/fsp_m.c +++ b/arch/x86/cpu/apollolake/fsp_m.c @@ -32,7 +32,10 @@ int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
node = dev_ofnode(dev); if (!ofnode_valid(node)) - return log_msg_ret("fsp-m settings", -ENOENT); + return log_msg_ret("node", -ENOENT); + node = ofnode_find_subnode(node, "fsp-m"); + if (!ofnode_valid(node)) + return log_msg_ret("fspm", -ENOENT);
ret = fsp_m_update_config_from_dtb(node, cfg); if (ret) diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index d66e128ae62..3c8fdf23809 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -174,6 +174,9 @@ */ fsp_s: fsp-s { }; + fsp_m: fsp-m { + u-boot,dm-spl; + };
nhlt { intel,dmic-channels = <4>; @@ -650,7 +653,9 @@ PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */ >; +};
+&fsp_m { fspm,package = <PACKAGE_BGA>; fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>; fspm,memory-down = <MEMORY_DOWN_YES>;