This board has been orphan for a while. (Emails to its maintainer have been bouncing.)
Because MPC8xx family is old enough, nobody would pick up the maintainership on it.
Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Wolfgang Denx wd@denx.de ---
board/adder/Makefile | 11 --- board/adder/adder.c | 108 --------------------------- board/adder/u-boot.lds | 79 -------------------- boards.cfg | 2 - doc/README.scrapyard | 1 + include/configs/Adder.h | 193 ------------------------------------------------ 6 files changed, 1 insertion(+), 393 deletions(-) delete mode 100644 board/adder/Makefile delete mode 100644 board/adder/adder.c delete mode 100644 board/adder/u-boot.lds delete mode 100644 include/configs/Adder.h
diff --git a/board/adder/Makefile b/board/adder/Makefile deleted file mode 100644 index 8dc505a..0000000 --- a/board/adder/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# Copyright (C) 2004 Arabella Software Ltd. -# Yuli Barcohen yuli@arabellasw.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := adder.o diff --git a/board/adder/adder.c b/board/adder/adder.c deleted file mode 100644 index 2ee7096..0000000 --- a/board/adder/adder.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (C) 2004-2005 Arabella Software Ltd. - * Yuli Barcohen yuli@arabellasw.com - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mpc8xx.h> -#if defined(CONFIG_OF_LIBFDT) - #include <libfdt.h> -#endif - -/* - * SDRAM is single Samsung K4S643232F-T70 chip (8MB) - * or single Micron MT48LC4M32B2TG-7 chip (16MB). - * Minimal CPU frequency is 40MHz. - */ -static uint sdram_table[] = { - /* Single read (offset 0x00 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00, - 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04, - - /* Burst read (offset 0x08 in UPM RAM) */ - 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00, - 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44, - 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35, - 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35, - - /* Single write (offset 0x18 in UPM RAM) */ - 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47, - 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Burst write (offset 0x20 in UPM RAM) */ - 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, - 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Refresh (offset 0x30 in UPM RAM) */ - 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, - 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04, - 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04, - - /* Exception (offset 0x3C in UPM RAM) */ - 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04 -}; - -phys_size_t initdram (int board_type) -{ - long int msize; - volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint)); - - /* Configure SDRAM refresh */ - memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */ - - memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */ - udelay(200); - - /* Run precharge from location 0x15 */ - memctl->memc_mar = 0x0; - memctl->memc_mcr = 0x80002115; - udelay(200); - - /* Run 8 refresh cycles */ - memctl->memc_mcr = 0x80002830; - udelay(200); - - /* Run MRS pattern from location 0x16 */ - memctl->memc_mar = 0x88; - memctl->memc_mcr = 0x80002116; - udelay(200); - - memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */ - memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM; - memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V; - - msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE); - memctl->memc_or1 |= ~(msize - 1); - - return msize; -} - -int checkboard( void ) -{ - puts("Board: Adder"); -#if defined(CONFIG_MPC885_FAMILY) - puts("87x\n"); -#elif defined(CONFIG_MPC866_FAMILY) - puts("II\n"); -#endif - - return 0; -} - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); - -} -#endif diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds deleted file mode 100644 index 38567d1..0000000 --- a/board/adder/u-boot.lds +++ /dev/null @@ -1,79 +0,0 @@ -/* - * (C) Copyright 2001-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Modified by Yuli Barcohen yuli@arabellasw.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - *(.text*) - . = ALIGN(16); - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} -ENTRY(_start) diff --git a/boards.cfg b/boards.cfg index 5f6e7bf..5e60162 100644 --- a/boards.cfg +++ b/boards.cfg @@ -1264,8 +1264,6 @@ Orphan powerpc mpc83xx - freescale mpc8360erdk Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov avorontsov@ru.mvista.com Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz andre.schwarz@matrix-vision.de Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz andre.schwarz@matrix-vision.de -Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen yuli@arabellasw.com -Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen yuli@arabellasw.com Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri tmarri@apm.com Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff dave@cray.com Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer travis.sawyer@sandburst.com diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 49cb4ca..fac4199 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +adder powerpc mpc8xx - - Yuli Barcohen yuli@arabellasw.com quad100hd powerpc ppc405ep - - Gary Jennejohn gljennjohn@googlemail.com lubbock arm pxa 36bf57b 2014-04-18 Kyle Harris kharris@nexus-tech.net EVB64260 powerpc mpc824x bb3aef9 2014-04-18 diff --git a/include/configs/Adder.h b/include/configs/Adder.h deleted file mode 100644 index 140f443..0000000 --- a/include/configs/Adder.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2004-2005 Arabella Software Ltd. - * Yuli Barcohen yuli@arabellasw.com - * - * Support for Analogue&Micro Adder boards family. - * Tested on AdderII and Adder87x. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) -#define CONFIG_MPC875 -#endif - -#define CONFIG_ADDER /* Analogue&Micro Adder board */ - -#define CONFIG_SYS_TEXT_BASE 0xFE000000 - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_BAUDRATE 38400 - -#define CONFIG_ETHER_ON_FEC1 -#define CONFIG_ETHER_ON_FEC2 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_MII_INIT 1 -#define FEC_ENET -#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ - -#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ -#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 -#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 -#ifdef CONFIG_MPC852T -#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000 -#else -#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 -#endif /* CONFIG_MPC852T */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - - -#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ -#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ -#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" - -#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ - -/*----------------------------------------------------------------------- - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_LONGHELP /* #undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ - -/*----------------------------------------------------------------------- - * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ - -#define CONFIG_SYS_MAMR 0x00002114 - -/* - * 4096 Up to 4096 SDRAM rows - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - */ -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ - -#define CONFIG_SYS_RESET_ADDRESS 0x09900000 - -/*----------------------------------------------------------------------- - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ -#ifdef CONFIG_BZIP2 -#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ -#else -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ -#endif /* CONFIG_BZIP2 */ - -/*----------------------------------------------------------------------- - * Flash organisation - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ - -/* Environment is in flash */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_OR0_PRELIM 0xFF000774 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) - -#define CONFIG_SYS_DIRECT_FLASH_TFTP - -/*----------------------------------------------------------------------- - * Internal Memory Map Register - */ -#define CONFIG_SYS_IMMR 0xFF000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Configuration registers - */ -#ifdef CONFIG_WATCHDOG -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ - SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ - SYPCR_SWF | SYPCR_SWP) -#endif /* CONFIG_WATCHDOG */ - -#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) - -/* TBSCR - Time Base Status and Control Register */ -#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) - -/* PISCR - Periodic Interrupt Status and Control */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/* PLPRCR - PLL, Low-Power, and Reset Control Register */ -/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */ - -/* SCCR - System Clock and reset Control Register */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR SCCR_RTSEL - -#define CONFIG_SYS_DER 0 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - -#endif /* __CONFIG_H */