B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies.
Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G
Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com --- arch/powerpc/cpu/mpc85xx/Makefile | 3 ++ arch/powerpc/cpu/mpc85xx/b4860_ids.c | 6 ++++ arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 45 +++++++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 21 +++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 2 +- drivers/net/fm/Makefile | 1 + 6 files changed, 77 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4c2b104..95994d3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -83,6 +83,7 @@ COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o +COBJS-$(CONFIG_PPC_B4420) += ddr-gen3.o COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o
@@ -100,6 +101,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o +COBJS-$(CONFIG_PPC_B4420) += b4860_ids.o COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
COBJS-$(CONFIG_QE) += qe_io.o @@ -134,6 +136,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o +COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
COBJS-y += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 7d33731..0f4e82e 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -55,11 +55,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif
+#ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { SET_SRIO_LIODN_1(1, 307), SET_SRIO_LIODN_1(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif
struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN @@ -76,10 +78,12 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 147), SET_DMA_LIODN(2, 227),
+#ifndef CONFIG_PPC_B4420 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), +#endif
/* SET_NEXUS_LIODN(557), -- not yet implemented */ }; @@ -93,8 +97,10 @@ struct liodn_id_table fman1_liodn_tbl[] = { SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 5, 93), +#ifndef CONFIG_PPC_B4420 SET_FMAN_RX_10G_LIODN(1, 0, 94), SET_FMAN_RX_10G_LIODN(1, 1, 95), +#endif }; int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); #endif diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index 0028280..bd32342 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -31,6 +31,7 @@ struct serdes_config { u8 lanes[SRDS_MAX_LANES]; };
+#ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, @@ -128,6 +129,50 @@ static struct serdes_config serdes2_cfg_tbl[] = { XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, {} }; +#endif + +#ifdef CONFIG_PPC_B4420 +static struct serdes_config serdes1_cfg_tbl[] = { + {0x0D, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x0E, {NONE, NONE, CPRI8, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x0F, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {0x18, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x1B, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x1E, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, + {0x21, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, + {0x3E, {NONE, NONE, CPRI6, CPRI5, + CPRI4, CPRI3, NONE, NONE} }, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, + {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, + {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x9A, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, + {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, + {} +}; +#endif + static struct serdes_config *serdes_cfg_tbl[] = { serdes1_cfg_tbl, serdes2_cfg_tbl, diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 856ae95..f957fa3 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -525,6 +525,27 @@ #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#elif defined(CONFIG_PPC_B4420) +#define CONFIG_SYS_PPC64 /* 64-bit core */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_A_004934 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 + #elif defined(CONFIG_PPC_B4860) #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 296b549..6a818c4 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1840,7 +1840,7 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 -#elif defined(CONFIG_PPC_B4860) +#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 7fbb50a..f191c79 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080.o COBJS-$(CONFIG_PPC_P5020) += p5020.o COBJS-$(CONFIG_PPC_P5040) += p5040.o COBJS-$(CONFIG_PPC_T4240) += t4240.o +COBJS-$(CONFIG_PPC_B4420) += b4860.o COBJS-$(CONFIG_PPC_B4860) += b4860.o endif