On 27 July 2015 at 11:45, Stephen Warren swarren@wwwdotorg.org wrote:
From: Thierry Reding treding@nvidia.com
Most peripherals on Tegra can do DMA only to the lower 32-bit address space, even on 64-bit SoCs. This limitation is typically overcome by the use of an IOMMU. Since the IOMMU is not entirely trivial to set up and serves no other purpose (I/O protection, ...) in U-Boot, restrict 64-bit Tegra SoCs to the lower 32-bit address space for RAM. This ensures that the physical addresses of buffers that are programmed into the various DMA engines are valid and don't alias to lower addresses.
Signed-off-by: Thierry Reding treding@nvidia.com Signed-off-by: Tom Warren twarren@nvidia.com Signed-off-by: Stephen Warren swarren@nvidia.com
These 3 patches are pre-requisites for T210 support (either compile-time or run-time) but don't seem to have been sent to the mailing lists recently.
arch/arm/mach-tegra/board2.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org