On 9/13/2023 1:05 PM, Heinrich Schuchardt wrote:
Am 13. September 2023 04:23:14 MESZ schrieb "Wu, Fei" fei2.wu@intel.com:
On 9/5/2023 6:09 PM, Fei Wu wrote:
In order to enable PCIe passthrough on qemu riscv, the physical memory range between 3GB and 4GB is reserved. Therefore if guest has 4GB ram, two ranges are created as [2G, 3G) and [4G, 7G), currently u-boot sets ram_top to 4G - 1 if the gd->ram_top is above 4G in board_get_usable_ram_top(), but that address is not backed by ram. This patch selects the lowest range instead.
I think multi-range memory layout is a common requirement, PCIe passthrough happens to be the first one to require it. Could anyone please take a look at this patch and give your comments?
Thanks, Fei.
Signed-off-by: Fei Wu fei2.wu@intel.com
arch/riscv/cpu/generic/dram.c | 2 +- configs/qemu-riscv64_smode_defconfig | 2 +-
We should consider all riscv64 defconfigs.
OK. I will update qemu-riscv64_defconfig, qemu-riscv64_smode_defconfig and qemu-riscv64_spl_defconfig.
Thanks, Fei.
Best regards
Heinrich
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 44e11bd56c..fb53a57b4e 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) {
- return fdtdec_setup_mem_size_base();
- return fdtdec_setup_mem_size_base_lowest();
}
int dram_init_banksize(void) diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index 1d0f021ade..de08a49dab 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -1,6 +1,6 @@ CONFIG_RISCV=y CONFIG_SYS_MALLOC_LEN=0x800000 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x20000